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git01.mediatek.com / filogic / uboot / 4a33795f89bfe869558345caa0cc43d52027e2a1 / . / arch / arm / dts / dra71-evm-u-boot.dtsi
blob: f13eadf6b687c307eb69f25ee6f48cecd4270185 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Lokesh Vutlae6734ae2017-08-21 12:51:00 +0530[diff] [blame]2/*
3 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
Lokesh Vutlae6734ae2017-08-21 12:51:00 +0530[diff] [blame]4 */
5
6#include "omap5-u-boot.dtsi"
Keerthy5d339ff2022-01-27 13:16:59 +0100[diff] [blame]7#include "dra7-ipu-common-early-boot.dtsi"
Lokesh Vutlae6734ae2017-08-21 12:51:00 +0530[diff] [blame]8
9&pcf_gpio_21{
10 u-boot,i2c-offset-len = <0>;
11};
12
13&pcf_hdmi{
14 u-boot,i2c-offset-len = <0>;
15};
16
17&cpsw_emac0 {
18 phy-handle = <&dp83867_0>;
19};
20
21&cpsw_emac1 {
22 phy-handle = <&dp83867_1>;
23};
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]24
25&mmc2_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]27};
28
29&mmc2_pins_hs {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]31};
32
33&mmc2_pins_ddr_rev20 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]35};
36
37&mmc2_iodelay_ddr_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]39};
40
41&mmc2_pins_hs200 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]43};
44
45&mmc2_iodelay_hs200_rev20_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]47};
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]48
49&omap_dwc3_1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]51};
52
53&usb1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]55 dr_mode = "peripheral";
56};
57
58&usb2_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]60};
61
62&usb3_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]64};