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Oleh Kravchenko4a2c0da2021-05-15 00:18:31 +03001// SPDX-License-Identifier: GPL-2.0+
2// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
3
4/dts-v1/;
5
6#include <dt-bindings/leds/common.h>
7
8#include "o4-imx6ull-nano.dtsi"
9
10/ {
11 model = "O4-iMX-NANO";
12 compatible = "out4,o4-imx-nano",
13 "out4,o4-imx6ull-nano",
14 "fsl,imx6ull";
15
16 aliases {
17 mmc1 = &usdhc1;
18 };
19
20 chosen {
21 stdout-path = &uart1;
22 };
23
24 leds {
25 compatible = "gpio-leds";
26
27 led@0 {
28 color = <LED_COLOR_ID_RED>;
29 gpios = <&pcf8574a 0 GPIO_ACTIVE_LOW>;
30 reg = <0>;
31 };
32
33 led@1 {
34 color = <LED_COLOR_ID_GREEN>;
35 gpios = <&pcf8574a 1 GPIO_ACTIVE_LOW>;
36 reg = <1>;
37 };
38
39 led@2 {
40 gpios = <&pcf8574a 2 GPIO_ACTIVE_LOW>;
41 color = <LED_COLOR_ID_BLUE>;
42 reg = <2>;
43 };
44
45 led@3 {
46 color = <LED_COLOR_ID_RED>;
47 gpios = <&pcf8574a 3 GPIO_ACTIVE_LOW>;
48 reg = <3>;
49 };
50
51 led@4 {
52 color = <LED_COLOR_ID_GREEN>;
53 gpios = <&pcf8574a 4 GPIO_ACTIVE_LOW>;
54 reg = <4>;
55 };
56
57 led@5 {
58 color = <LED_COLOR_ID_BLUE>;
59 gpios = <&pcf8574a 5 GPIO_ACTIVE_LOW>;
60 reg = <5>;
61 };
62 };
63
64 usbotg1_vbus: reg_usbotg1_vbus {
65 compatible = "regulator-fixed";
66 enable-active-high;
67 gpio = <&pcf8574a 6 GPIO_ACTIVE_HIGH>;
68 regulator-max-microvolt = <5000000>;
69 regulator-min-microvolt = <5000000>;
70 regulator-name = "usb0";
71 };
72
73 usbotg2_vbus: reg_usbotg2_vbus {
74 compatible = "regulator-fixed";
75 enable-active-high;
76 gpio = <&pcf8574a 7 GPIO_ACTIVE_HIGH>;
77 regulator-max-microvolt = <5000000>;
78 regulator-min-microvolt = <5000000>;
79 regulator-name = "usb1";
80 };
81};
82
83&iomuxc {
84 pinctrl_uart1: uart1grp {
85 fsl,pins = <
86 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
87 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
88 >;
89 };
90
91 pinctrl_usdhc1: usdhc1grp {
92 fsl,pins = <
93 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10069
94 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
95 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
96 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
97 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
98 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
99 MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
100 >;
101 };
102
103 pinctrl_mdio: mdiogrp {
104 fsl,pins = <
105 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
106 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
107 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0xb0b0 /* RST */
108 >;
109 };
110
111 pinctrl_i2c2: i2c2grp {
112 fsl,pins = <
113 MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0
114 MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0
115 >;
116 };
117
118 pinctrl_i2c2_gpio: i2c2gpiogrp {
119 fsl,pins = <
120 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b8b0
121 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b8b0
122 >;
123 };
124
125 pinctrl_can1: can1grp {
126 fsl,pins = <
127 MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020
128 MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020
129 >;
130 };
131
132 pinctrl_uart2: uart2grp {
133 fsl,pins = <
134 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
135 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
136 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
137 >;
138 };
139};
140
141&uart1 {
142 pinctrl-0 = <&pinctrl_uart1>;
143 pinctrl-names = "default";
144 status = "okay";
145};
146
147&usdhc1 {
148 bus-width = <4>;
149 no-1-8-v;
150 pinctrl-0 = <&pinctrl_usdhc1>;
151 pinctrl-names = "default";
152 status = "okay";
153 wakeup-source;
154};
155
156&fec1 {
157 phy-handle = <&phy0>;
158 phy-mode = "rmii";
159 pinctrl-0 = <&pinctrl_fec1>;
160 pinctrl-names = "default";
161 status = "okay";
162};
163
164&fec2 {
165 phy-handle = <&phy1>;
166 phy-mode = "rmii";
167 phy-reset-duration = <250>;
168 phy-reset-post-delay = <100>;
169 phy-reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
170 pinctrl-0 = <&pinctrl_fec2 &pinctrl_mdio>;
171 pinctrl-names = "default";
172 status = "okay";
173
174 mdio {
175 #address-cells = <1>;
176 #size-cells = <0>;
177
178 phy0: ethernet-phy@0 {
179 clocks = <&clks IMX6UL_CLK_ENET_REF>;
180 clock-names = "rmii-ref";
181 interrupt-parent = <&gpio5>;
182 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
183 pinctrl-0 = <&pinctrl_phy0_irq>;
184 pinctrl-names = "default";
185 reg = <0>;
186 };
187
188 phy1: ethernet-phy@1 {
189 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
190 clock-names = "rmii-ref";
191 interrupt-parent = <&gpio5>;
192 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
193 pinctrl-0 = <&pinctrl_phy1_irq>;
194 pinctrl-names = "default";
195 reg = <1>;
196 };
197 };
198};
199
200&usbotg1 {
201 dr_mode = "host";
202 status = "okay";
203 vbus-supply = <&usbotg1_vbus>;
204};
205
206&usbotg2 {
207 dr_mode = "host";
208 status = "okay";
209 vbus-supply = <&usbotg2_vbus>;
210};
211
212&i2c2 {
213 clock_frequency = <100000>;
214 pinctrl-0 = <&pinctrl_i2c2>;
215 pinctrl-1 = <&pinctrl_i2c2_gpio>;
216 pinctrl-names = "default", "gpio";
217 scl-gpios = <&gpio4 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
218 sda-gpios = <&gpio4 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
219 status = "okay";
220
221 pcf8574a: gpio@38 {
222 compatible = "nxp,pcf8574a";
223 #gpio-cells = <2>;
224 gpio-controller;
225 reg = <0x38>;
226 };
227};
228
229&can1 {
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_can1>;
232 status = "okay";
233};
234
235&uart2 {
236 linux,rs485-enabled-at-boot-time;
237 pinctrl-0 = <&pinctrl_uart2>;
238 pinctrl-names = "default";
239 status = "okay";
240 uart-has-rtscts;
241};