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Sergey Kubushyne8f39122007-08-10 20:26:18 +02001/*
2 * National Semiconductor DP83848 PHY Driver for TI DaVinci
3 * (TMS320DM644x) based boards.
4 *
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 *
7 * --------------------------------------------------------
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <net.h>
30#include <dp83848.h>
31#include <asm/arch/emac_defs.h>
32
33#ifdef CONFIG_DRIVER_TI_EMAC
34
35#ifdef CONFIG_CMD_NET
36
37int dp83848_is_phy_connected(int phy_addr)
38{
39 u_int16_t id1, id2;
40
Sandeep Paulraj4b26f052008-08-31 00:39:46 +020041 if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
Sergey Kubushyne8f39122007-08-10 20:26:18 +020042 return(0);
Sandeep Paulraj4b26f052008-08-31 00:39:46 +020043 if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
Sergey Kubushyne8f39122007-08-10 20:26:18 +020044 return(0);
45
46 if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
47 return(1);
48
49 return(0);
50}
51
52int dp83848_get_link_speed(int phy_addr)
53{
54 u_int16_t tmp;
55 volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR;
56
Sandeep Paulraj4b26f052008-08-31 00:39:46 +020057 if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
Sergey Kubushyne8f39122007-08-10 20:26:18 +020058 return(0);
59
60 if (!(tmp & DP83848_LINK_STATUS)) /* link up? */
61 return(0);
62
Sandeep Paulraj4b26f052008-08-31 00:39:46 +020063 if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
Sergey Kubushyne8f39122007-08-10 20:26:18 +020064 return(0);
65
66 /* Speed doesn't matter, there is no setting for it in EMAC... */
67 if (tmp & DP83848_SPEED) {
68 if (tmp & DP83848_DUPLEX) {
69 /* set DM644x EMAC for Full Duplex */
70 emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
71 } else {
72 /*set DM644x EMAC for Half Duplex */
73 emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
74 }
75
76 return(1);
77 } else {
78 if (tmp & DP83848_DUPLEX) {
79 /* set DM644x EMAC for Full Duplex */
80 emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
81 } else {
82 /*set DM644x EMAC for Half Duplex */
83 emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
84 }
85
86 return(1);
87 }
88
89 return(0);
90}
91
92
93int dp83848_init_phy(int phy_addr)
94{
95 int ret = 1;
96
97 if (!dp83848_get_link_speed(phy_addr)) {
98 /* Try another time */
99 udelay(100000);
100 ret = dp83848_get_link_speed(phy_addr);
101 }
102
103 /* Disable PHY Interrupts */
Sandeep Paulraj4b26f052008-08-31 00:39:46 +0200104 davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200105
106 return(ret);
107}
108
109
110int dp83848_auto_negotiate(int phy_addr)
111{
112 u_int16_t tmp;
113
114
Sandeep Paulraj4b26f052008-08-31 00:39:46 +0200115 if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200116 return(0);
117
118 /* Restart Auto_negotiation */
119 tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */
120 tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */
Sandeep Paulraj4b26f052008-08-31 00:39:46 +0200121 davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200122
123 /* Set the Auto_negotiation Advertisement Register
124 * MII advertising for Next page, 100BaseTxFD and HD,
125 * 10BaseTFD and HD, IEEE 802.3
126 */
127 tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
Wolfgang Denka1be4762008-05-20 16:00:29 +0200128 DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
Sandeep Paulraj4b26f052008-08-31 00:39:46 +0200129 davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200130
131
132 /* Read Control Register */
Sandeep Paulraj4b26f052008-08-31 00:39:46 +0200133 if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200134 return(0);
135
136 tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
Sandeep Paulraj4b26f052008-08-31 00:39:46 +0200137 davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200138
139 /* Restart Auto_negotiation */
140 tmp |= DP83848_RESTART_AUTONEG;
Sandeep Paulraj4b26f052008-08-31 00:39:46 +0200141 davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200142
143 /*check AutoNegotiate complete */
144 udelay(10000);
Sandeep Paulraj4b26f052008-08-31 00:39:46 +0200145 if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200146 return(0);
147
148 if (!(tmp & DP83848_AUTONEG_COMP))
149 return(0);
150
151 return (dp83848_get_link_speed(phy_addr));
152}
153
154#endif /* CONFIG_CMD_NET */
155
156#endif /* CONFIG_DRIVER_ETHER */