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git01.mediatek.com / filogic / uboot / 49ebcb53b9927d09917e2004722625606be7e468 / . / board / mx1ads / lowlevel_init.S
blob: 6967fb2b414c9c59c8f9fabbcc07e6a29da132c4 [file] [log] [blame]
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]1/*
wdenk336b2bc2005-04-02 23:52:25 +0000[diff] [blame]2 * board/mx1ads/lowlevel_init.S
wdenk9e930b62004-06-19 21:19:10 +0000[diff] [blame]3 *
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]4 * (c) Copyright 2004
5 * Techware Information Technology, Inc.
6 * http://www.techware.com.tw/
7 *
8 * Ming-Len Wu <minglen_wu@techware.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <config.h>
27#include <version.h>
28
29#define SDCTL0 0x221000
30#define SDCTL1 0x221004
31
32
33_TEXT_BASE:
34 .word TEXT_BASE
35
wdenk336b2bc2005-04-02 23:52:25 +0000[diff] [blame]36.globl lowlevel_init
37lowlevel_init:
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]38/* memory controller init */
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]39
40 ldr r1, =SDCTL0
41
42/* Set Precharge Command */
43
44 ldr r3, =0x92120200
45/* ldr r3, =0x92120251
46*/
47 str r3, [r1]
48
49/* Issue Precharge All Commad */
50 ldr r3, =0x8200000
51 ldr r2, [r3]
wdenk9e930b62004-06-19 21:19:10 +0000[diff] [blame]52
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]53/* Set AutoRefresh Command */
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]54 ldr r3, =0xA2120200
55 str r3, [r1]
56
57/* Issue AutoRefresh Command */
58 ldr r3, =0x8000000
59 ldr r2, [r3]
60 ldr r2, [r3]
61 ldr r2, [r3]
62 ldr r2, [r3]
63 ldr r2, [r3]
64 ldr r2, [r3]
65 ldr r2, [r3]
66 ldr r2, [r3]
wdenk9e930b62004-06-19 21:19:10 +0000[diff] [blame]67
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]68/* Set Mode Register */
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]69 ldr r3, =0xB2120200
70 str r3, [r1]
wdenk9e930b62004-06-19 21:19:10 +0000[diff] [blame]71
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]72/* Issue Mode Register Command */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]73 ldr r3, =0x08111800 /* Mode Register Value */
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]74 ldr r2, [r3]
75
76/* Set Normal Mode */
77 ldr r3, =0x82124200
78 str r3, [r1]
79
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]80/* everything is fine now */
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]81 mov pc, lr