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git01.mediatek.com / filogic / uboot / 49e7d77be0c916f39ee299193e0061785479160e / . / drivers / pinctrl / rockchip / pinctrl_rk3036.c
blob: 581b09688c59e04548490b066cd5c6b1269f1294 [file] [log] [blame]
huang lin4ccd9952015-11-17 14:20:20 +0800[diff] [blame]1/*
2 * Pinctrl driver for Rockchip 3036 SoCs
3 * (C) Copyright 2015 Rockchip Electronics Co., Ltd
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <syscon.h>
12#include <asm/io.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/grf_rk3036.h>
15#include <asm/arch/hardware.h>
16#include <asm/arch/periph.h>
17#include <dm/pinctrl.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21struct rk3036_pinctrl_priv {
22 struct rk3036_grf *grf;
23};
24
25static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id)
26{
27 switch (pwm_id) {
28 case PERIPH_ID_PWM0:
29 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK << GPIO0D2_SHIFT,
30 GPIO0D2_PWM0 << GPIO0D2_SHIFT);
31 break;
32 case PERIPH_ID_PWM1:
33 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK << GPIO0A0_SHIFT,
34 GPIO0A0_PWM1 << GPIO0A0_SHIFT);
35 break;
36 case PERIPH_ID_PWM2:
37 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK << GPIO0A1_SHIFT,
38 GPIO0A1_PWM2 << GPIO0A1_SHIFT);
39 break;
40 case PERIPH_ID_PWM3:
41 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK << GPIO0D3_SHIFT,
42 GPIO0D3_PWM3 << GPIO0D3_SHIFT);
43 break;
44 default:
45 debug("pwm id = %d iomux error!\n", pwm_id);
46 break;
47 }
48}
49
50static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id)
51{
52 switch (i2c_id) {
53 case PERIPH_ID_I2C0:
54 rk_clrsetreg(&grf->gpio0a_iomux,
55 GPIO0A1_MASK << GPIO0A1_SHIFT |
56 GPIO0A0_MASK << GPIO0A0_SHIFT,
57 GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
58 GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
59
60 break;
61 case PERIPH_ID_I2C1:
62 rk_clrsetreg(&grf->gpio0a_iomux,
63 GPIO0A3_MASK << GPIO0A3_SHIFT |
64 GPIO0A2_MASK << GPIO0A2_SHIFT,
65 GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
66 GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
67 break;
68 case PERIPH_ID_I2C2:
69 rk_clrsetreg(&grf->gpio2c_iomux,
70 GPIO2C5_MASK << GPIO2C5_SHIFT |
71 GPIO2C4_MASK << GPIO2C4_SHIFT,
72 GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
73 GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
74
75 break;
76 }
77}
78
79static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs)
80{
81 switch (cs) {
82 case 0:
83 rk_clrsetreg(&grf->gpio1d_iomux,
84 GPIO1D6_MASK << GPIO1D6_SHIFT,
85 GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT);
86 break;
87 case 1:
88 rk_clrsetreg(&grf->gpio1d_iomux,
89 GPIO1D7_MASK << GPIO1D7_SHIFT,
90 GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT);
91 break;
92 }
93 rk_clrsetreg(&grf->gpio1d_iomux,
94 GPIO1D5_MASK << GPIO1D5_SHIFT |
95 GPIO1D4_MASK << GPIO1D4_SHIFT,
96 GPIO1D5_SPI_TXD << GPIO1D5_SHIFT |
97 GPIO1D4_SPI_RXD << GPIO1D4_SHIFT);
98
99 rk_clrsetreg(&grf->gpio2a_iomux,
100 GPIO2A0_MASK << GPIO2A0_SHIFT,
101 GPIO2A0_SPI_CLK << GPIO2A0_SHIFT);
102}
103
104static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id)
105{
106 switch (uart_id) {
107 case PERIPH_ID_UART0:
108 rk_clrsetreg(&grf->gpio0c_iomux,
109 GPIO0C3_MASK << GPIO0C3_SHIFT |
110 GPIO0C2_MASK << GPIO0C2_SHIFT |
111 GPIO0C1_MASK << GPIO0C1_SHIFT |
112 GPIO0C0_MASK << GPIO0C0_SHIFT,
113 GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT |
114 GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT |
115 GPIO0C1_UART0_SIN << GPIO0C1_SHIFT |
116 GPIO0C0_UART0_SOUT << GPIO0C0_SHIFT);
117 break;
118 case PERIPH_ID_UART1:
119 rk_clrsetreg(&grf->gpio2c_iomux,
120 GPIO2C7_MASK << GPIO2C7_SHIFT |
121 GPIO2C6_MASK << GPIO2C6_SHIFT,
122 GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT |
123 GPIO2C6_UART1_SIN << GPIO2C6_SHIFT);
124 break;
125 case PERIPH_ID_UART2:
126 rk_clrsetreg(&grf->gpio1c_iomux,
127 GPIO1C3_MASK << GPIO1C3_SHIFT |
128 GPIO1C2_MASK << GPIO1C2_SHIFT,
129 GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
130 GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
131 break;
132 }
133}
134
135static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id)
136{
137 switch (mmc_id) {
138 case PERIPH_ID_EMMC:
139 rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
140 GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
141 GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
142 GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
143 GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
144 GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
145 GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
146 GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
147 GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
148 rk_clrsetreg(&grf->gpio2a_iomux,
149 GPIO2A4_MASK << GPIO2A4_SHIFT |
150 GPIO2A1_MASK << GPIO2A1_SHIFT,
151 GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT |
152 GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT);
153 break;
154 case PERIPH_ID_SDCARD:
155 rk_clrsetreg(&grf->gpio1c_iomux, 0xffff,
156 GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT |
157 GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT |
158 GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT |
159 GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT |
160 GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT |
161 GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT);
162 break;
163 }
164}
165
166static int rk3036_pinctrl_request(struct udevice *dev, int func, int flags)
167{
168 struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
169
170 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
171 switch (func) {
172 case PERIPH_ID_PWM0:
173 case PERIPH_ID_PWM1:
174 case PERIPH_ID_PWM2:
175 case PERIPH_ID_PWM3:
176 pinctrl_rk3036_pwm_config(priv->grf, func);
177 break;
178 case PERIPH_ID_I2C0:
179 case PERIPH_ID_I2C1:
180 case PERIPH_ID_I2C2:
181 pinctrl_rk3036_i2c_config(priv->grf, func);
182 break;
183 case PERIPH_ID_SPI0:
184 pinctrl_rk3036_spi_config(priv->grf, flags);
185 break;
186 case PERIPH_ID_UART0:
187 case PERIPH_ID_UART1:
188 case PERIPH_ID_UART2:
189 pinctrl_rk3036_uart_config(priv->grf, func);
190 break;
191 case PERIPH_ID_SDMMC0:
192 case PERIPH_ID_SDMMC1:
193 pinctrl_rk3036_sdmmc_config(priv->grf, func);
194 break;
195 default:
196 return -EINVAL;
197 }
198
199 return 0;
200}
201
202static int rk3036_pinctrl_get_periph_id(struct udevice *dev,
203 struct udevice *periph)
204{
205 u32 cell[3];
206 int ret;
207
208 ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
209 "interrupts", cell, ARRAY_SIZE(cell));
210 if (ret < 0)
211 return -EINVAL;
212
213 switch (cell[1]) {
214 case 14:
215 return PERIPH_ID_SDCARD;
216 case 16:
217 return PERIPH_ID_EMMC;
218 case 20:
219 return PERIPH_ID_UART0;
220 case 21:
221 return PERIPH_ID_UART1;
222 case 22:
223 return PERIPH_ID_UART2;
224 case 23:
225 return PERIPH_ID_SPI0;
226 case 24:
227 return PERIPH_ID_I2C0;
228 case 25:
229 return PERIPH_ID_I2C1;
230 case 26:
231 return PERIPH_ID_I2C2;
232 case 30:
233 return PERIPH_ID_PWM0;
234 }
235 return -ENOENT;
236}
237
238static int rk3036_pinctrl_set_state_simple(struct udevice *dev,
239 struct udevice *periph)
240{
241 int func;
242
243 func = rk3036_pinctrl_get_periph_id(dev, periph);
244 if (func < 0)
245 return func;
246 return rk3036_pinctrl_request(dev, func, 0);
247}
248
249static struct pinctrl_ops rk3036_pinctrl_ops = {
250 .set_state_simple = rk3036_pinctrl_set_state_simple,
251 .request = rk3036_pinctrl_request,
252 .get_periph_id = rk3036_pinctrl_get_periph_id,
253};
254
255static int rk3036_pinctrl_probe(struct udevice *dev)
256{
257 struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
258
259 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
260 debug("%s: grf=%p\n", __func__, priv->grf);
261 return 0;
262}
263
264static const struct udevice_id rk3036_pinctrl_ids[] = {
265 { .compatible = "rockchip,rk3036-pinctrl" },
266 { }
267};
268
269U_BOOT_DRIVER(pinctrl_rk3036) = {
270 .name = "pinctrl_rk3036",
271 .id = UCLASS_PINCTRL,
272 .of_match = rk3036_pinctrl_ids,
273 .priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv),
274 .ops = &rk3036_pinctrl_ops,
275 .probe = rk3036_pinctrl_probe,
276};