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git01.mediatek.com / filogic / uboot / 49e7d77be0c916f39ee299193e0061785479160e / . / board / bachmann / ot1200 / ot1200_spl.c
blob: f651a40a49e272410a2114372feb2db8a15a9764 [file] [log] [blame]
Christian Gmeinerf4781292015-01-19 17:26:49 +0100[diff] [blame]1/*
2 * Copyright (C) 2015, Bachmann electronic GmbH
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <spl.h>
9#include <asm/arch/mx6-ddr.h>
10
11DECLARE_GLOBAL_DATA_PTR;
12
13/* Configure MX6Q/DUAL mmdc DDR io registers */
14static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
15 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
16 .dram_sdclk_0 = 0x00000028,
17 .dram_sdclk_1 = 0x00000028,
18 .dram_cas = 0x00000028,
19 .dram_ras = 0x00000028,
20 .dram_reset = 0x00000028,
21 /* SDCKE[0:1]: 100k pull-up */
22 .dram_sdcke0 = 0x00003000,
23 .dram_sdcke1 = 0x00003000,
24 /* SDBA2: pull-up disabled */
25 .dram_sdba2 = 0x00000000,
26 /* SDODT[0:1]: 100k pull-up, 48 ohm */
27 .dram_sdodt0 = 0x00000028,
28 .dram_sdodt1 = 0x00000028,
29 /* SDQS[0:7]: Differential input, 48 ohm */
30 .dram_sdqs0 = 0x00000028,
31 .dram_sdqs1 = 0x00000028,
32 .dram_sdqs2 = 0x00000028,
33 .dram_sdqs3 = 0x00000028,
34 .dram_sdqs4 = 0x00000028,
35 .dram_sdqs5 = 0x00000028,
36 .dram_sdqs6 = 0x00000028,
37 .dram_sdqs7 = 0x00000028,
38 /* DQM[0:7]: Differential input, 48 ohm */
39 .dram_dqm0 = 0x00000028,
40 .dram_dqm1 = 0x00000028,
41 .dram_dqm2 = 0x00000028,
42 .dram_dqm3 = 0x00000028,
43 .dram_dqm4 = 0x00000028,
44 .dram_dqm5 = 0x00000028,
45 .dram_dqm6 = 0x00000028,
46 .dram_dqm7 = 0x00000028,
47};
48
49/* Configure MX6Q/DUAL mmdc GRP io registers */
50static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = {
51 /* DDR3 */
52 .grp_ddr_type = 0x000c0000,
53 .grp_ddrmode_ctl = 0x00020000,
54 /* Disable DDR pullups */
55 .grp_ddrpke = 0x00000000,
56 /* ADDR[00:16], SDBA[0:1]: 48 ohm */
57 .grp_addds = 0x00000028,
58 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */
59 .grp_ctlds = 0x00000028,
60 /* DATA[00:63]: Differential input, 48 ohm */
61 .grp_ddrmode = 0x00020000,
62 .grp_b0ds = 0x00000028,
63 .grp_b1ds = 0x00000028,
64 .grp_b2ds = 0x00000028,
65 .grp_b3ds = 0x00000028,
66 .grp_b4ds = 0x00000028,
67 .grp_b5ds = 0x00000028,
68 .grp_b6ds = 0x00000028,
69 .grp_b7ds = 0x00000028,
70};
71
72static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
73 /* Width of data bus: 0=16, 1=32, 2=64 */
74 .dsize = 2,
75 /* config for full 4GB range so that get_mem_size() works */
76 .cs_density = 32, /* 32Gb per CS */
77 /* Single chip select */
78 .ncs = 1,
79 .cs1_mirror = 0, /* war 0 */
80 .rtt_wr = 1, /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
81 .rtt_nom = 1, /* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */
82 .walat = 1, /* Write additional latency */
83 .ralat = 5, /* Read additional latency */
84 .mif3_mode = 3, /* Command prediction working mode */
85 .bi_on = 1, /* Bank interleaving enabled */ /* war 1 */
86 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
87 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
88};
89
90/* MT41K128M16JT-125 */
91static struct mx6_ddr3_cfg micron_2gib_1600 = {
92 .mem_speed = 1600,
93 .density = 2,
94 .width = 16,
95 .banks = 8,
96 .rowaddr = 14,
97 .coladdr = 10,
98 .pagesz = 2,
99 .trcd = 1375,
100 .trcmin = 4875,
101 .trasmin = 3500,
102 .SRT = 1,
103};
104
105static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = {
106 /* write leveling calibration determine */
107 .p0_mpwldectrl0 = 0x00260025,
108 .p0_mpwldectrl1 = 0x00270021,
109 .p1_mpwldectrl0 = 0x00180034,
110 .p1_mpwldectrl1 = 0x00180024,
111 /* Read DQS Gating calibration */
112 .p0_mpdgctrl0 = 0x04380344,
113 .p0_mpdgctrl1 = 0x0330032C,
114 .p1_mpdgctrl0 = 0x0338033C,
115 .p1_mpdgctrl1 = 0x032C0300,
116 /* Read Calibration: DQS delay relative to DQ read access */
117 .p0_mprddlctl = 0x3C2E3238,
118 .p1_mprddlctl = 0x3A2E303C,
119 /* Write Calibration: DQ/DM delay relative to DQS write access */
120 .p0_mpwrdlctl = 0x36384036,
121 .p1_mpwrdlctl = 0x442E4438,
122};
123
124static void ot1200_spl_dram_init(void)
125{
126 mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs);
127 mx6_dram_cfg(&ot1200_ddr_sysinfo, &micron_2gib_1600_mmdc_calib,
128 &micron_2gib_1600);
129}
130
131/*
132 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
133 * - we have a stack and a place to store GD, both in SRAM
134 * - no variable global data is available
135 */
136void board_init_f(ulong dummy)
137{
138 /* setup AIPS and disable watchdog */
139 arch_cpu_init();
140
141 /* iomux and setup of i2c */
142 board_early_init_f();
143
144 /* setup GP timer */
145 timer_init();
146
147 /* UART clocks enabled and gd valid - init serial console */
148 preloader_console_init();
149
150 /* configure MMDC for SDRAM width/size and per-model calibration */
151 ot1200_spl_dram_init();
152
153 /* Clear the BSS. */
154 memset(__bss_start, 0, __bss_end - __bss_start);
155
156 /* load/boot image from boot device */
157 board_init_r(NULL, 0);
158}