blob: 9ac7ca923c7b2f3201097e811decbf31a0354dd1 [file] [log] [blame]
Peng Fan692f9432018-11-20 10:19:57 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3* Copyright 2018 NXP
4*/
5
6#include <common.h>
7#include <errno.h>
8#include <asm/io.h>
9#include <asm/arch/ddr.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/ddr.h>
12#include <asm/arch/lpddr4_define.h>
13
14static inline void poll_pmu_message_ready(void)
15{
16 unsigned int reg;
17
18 do {
19 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
20 } while (reg & 0x1);
21}
22
23static inline void ack_pmu_message_receive(void)
24{
25 unsigned int reg;
26
27 reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0);
28
29 do {
30 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
31 } while (!(reg & 0x1));
32
33 reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1);
34}
35
36static inline unsigned int get_mail(void)
37{
38 unsigned int reg;
39
40 poll_pmu_message_ready();
41
42 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
43
44 ack_pmu_message_receive();
45
46 return reg;
47}
48
49static inline unsigned int get_stream_message(void)
50{
51 unsigned int reg, reg2;
52
53 poll_pmu_message_ready();
54
55 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
56
57 reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034);
58
59 reg2 = (reg2 << 16) | reg;
60
61 ack_pmu_message_receive();
62
63 return reg2;
64}
65
66static inline void decode_major_message(unsigned int mail)
67{
68 debug("[PMU Major message = 0x%08x]\n", mail);
69}
70
71static inline void decode_streaming_message(void)
72{
73 unsigned int string_index, arg __maybe_unused;
74 int i = 0;
75
76 string_index = get_stream_message();
77 debug("PMU String index = 0x%08x\n", string_index);
78 while (i < (string_index & 0xffff)) {
79 arg = get_stream_message();
80 debug("arg[%d] = 0x%08x\n", i, arg);
81 i++;
82 }
83
84 debug("\n");
85}
86
Frieder Schrempf2a9b1f52019-12-11 10:01:19 +000087int wait_ddrphy_training_complete(void)
Peng Fan692f9432018-11-20 10:19:57 +000088{
89 unsigned int mail;
90
91 while (1) {
92 mail = get_mail();
93 decode_major_message(mail);
94 if (mail == 0x08) {
95 decode_streaming_message();
96 } else if (mail == 0x07) {
97 debug("Training PASS\n");
Frieder Schrempf2a9b1f52019-12-11 10:01:19 +000098 return 0;
Peng Fan692f9432018-11-20 10:19:57 +000099 } else if (mail == 0xff) {
Frieder Schrempf2a9b1f52019-12-11 10:01:19 +0000100 debug("Training FAILED\n");
101 return -1;
Peng Fan692f9432018-11-20 10:19:57 +0000102 }
103 }
104}
105
106void ddrphy_init_set_dfi_clk(unsigned int drate)
107{
108 switch (drate) {
Peng Fan49dbcee2019-12-30 09:58:52 +0800109 case 4000:
110 dram_pll_init(MHZ(1000));
111 dram_disable_bypass();
112 break;
Peng Fan692f9432018-11-20 10:19:57 +0000113 case 3200:
114 dram_pll_init(MHZ(800));
115 dram_disable_bypass();
116 break;
117 case 3000:
118 dram_pll_init(MHZ(750));
119 dram_disable_bypass();
120 break;
121 case 2400:
122 dram_pll_init(MHZ(600));
123 dram_disable_bypass();
124 break;
125 case 1600:
126 dram_pll_init(MHZ(400));
127 dram_disable_bypass();
128 break;
Jacky Baid62ddc12019-08-08 09:59:08 +0000129 case 1066:
130 dram_pll_init(MHZ(266));
131 dram_disable_bypass();
132 break;
Peng Fan692f9432018-11-20 10:19:57 +0000133 case 667:
134 dram_pll_init(MHZ(167));
135 dram_disable_bypass();
136 break;
137 case 400:
138 dram_enable_bypass(MHZ(400));
139 break;
140 case 100:
141 dram_enable_bypass(MHZ(100));
142 break;
143 default:
144 return;
145 }
146}
147
148void ddrphy_init_read_msg_block(enum fw_type type)
149{
150}
151
152void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr,
153 unsigned int mr_data)
154{
155 unsigned int tmp;
156 /*
157 * 1. Poll MRSTAT.mr_wr_busy until it is 0.
158 * This checks that there is no outstanding MR transaction.
159 * No writes should be performed to MRCTRL0 and MRCTRL1 if
160 * MRSTAT.mr_wr_busy = 1.
161 */
162 do {
163 tmp = reg32_read(DDRC_MRSTAT(0));
164 } while (tmp & 0x1);
165 /*
166 * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and
167 * (for MRWs) MRCTRL1.mr_data to define the MR transaction.
168 */
169 reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4));
170 reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
171 reg32setbit(DDRC_MRCTRL0(0), 31);
172}
173
174unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
175{
176 unsigned int tmp;
177
178 reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
179 do {
180 tmp = reg32_read(DDRC_MRSTAT(0));
181 } while (tmp & 0x1);
182
183 reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
184 reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
185 reg32setbit(DDRC_MRCTRL0(0), 31);
186 do {
187 tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
188 } while ((tmp & 0x8) == 0);
189 tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
190 tmp = tmp & 0xff;
191 reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
192
193 return tmp;
194}