| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * Interrupt vector number definitions to ease the |
| 25 | * 405 -- 440 porting pain ;-) |
| 26 | * |
| 27 | * NOTE: They're not all here yet ... update as needed. |
| 28 | * |
| 29 | */ |
| 30 | |
| 31 | #ifndef _VECNUMS_H_ |
| 32 | #define _VECNUMS_H_ |
| 33 | |
| Marian Balakowicz | 49d0eee | 2006-06-30 16:30:46 +0200 | [diff] [blame^] | 34 | #if defined(CONFIG_440SPE) |
| 35 | /* UIC 0 */ |
| 36 | #define VECNUM_U0 0 /* UART0 */ |
| 37 | #define VECNUM_U1 1 /* UART1 */ |
| 38 | #define VECNUM_IIC0 2 /* IIC0 */ |
| 39 | #define VECNUM_IIC1 3 /* IIC1 */ |
| 40 | #define VECNUM_PIM 4 /* PCI inbound message */ |
| 41 | #define VECNUM_PCRW 5 /* PCI command reg write */ |
| 42 | #define VECNUM_PPM 6 /* PCI power management */ |
| 43 | #define VECNUM_MSI0 7 /* PCI MSI level 0 */ |
| 44 | #define VECNUM_MSI1 8 /* PCI MSI level 0 */ |
| 45 | #define VECNUM_MSI2 9 /* PCI MSI level 0 */ |
| 46 | #define VECNUM_D0 12 /* DMA channel 0 */ |
| 47 | #define VECNUM_D1 13 /* DMA channel 1 */ |
| 48 | #define VECNUM_D2 14 /* DMA channel 2 */ |
| 49 | #define VECNUM_D3 15 /* DMA channel 3 */ |
| 50 | #define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ |
| 51 | #define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ |
| 52 | |
| 53 | /* UIC 1 */ |
| 54 | #define VECNUM_MS (32 + 1 ) /* MAL SERR */ |
| 55 | #define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */ |
| 56 | #define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */ |
| 57 | #define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */ |
| 58 | #define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */ |
| 59 | #define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */ |
| 60 | #define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */ |
| 61 | #define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */ |
| 62 | #define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */ |
| 63 | #define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */ |
| 64 | #define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ |
| 65 | #define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ |
| 66 | |
| 67 | /* UIC 2 */ |
| 68 | #define VECNUM_EIR5 (62 + 24) /* External interrupt 5 */ |
| 69 | #define VECNUM_EIR4 (62 + 25) /* External interrupt 4 */ |
| 70 | #define VECNUM_EIR3 (62 + 26) /* External interrupt 3 */ |
| 71 | #define VECNUM_EIR2 (62 + 27) /* External interrupt 2 */ |
| 72 | #define VECNUM_EIR1 (62 + 28) /* External interrupt 1 */ |
| 73 | #define VECNUM_EIR0 (62 + 29) /* External interrupt 0 */ |
| 74 | |
| 75 | #elif defined(CONFIG_440SP) |
| Stefan Roese | 9964474 | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 76 | |
| 77 | /* UIC 0 */ |
| 78 | #define VECNUM_U0 0 /* UART0 */ |
| 79 | #define VECNUM_U1 1 /* UART1 */ |
| 80 | #define VECNUM_IIC0 2 /* IIC0 */ |
| 81 | #define VECNUM_IIC1 3 /* IIC1 */ |
| 82 | #define VECNUM_PIM 4 /* PCI inbound message */ |
| 83 | #define VECNUM_PCRW 5 /* PCI command reg write */ |
| 84 | #define VECNUM_PPM 6 /* PCI power management */ |
| 85 | #define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ |
| 86 | #define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ |
| 87 | |
| 88 | /* UIC 1 */ |
| 89 | #define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */ |
| 90 | #define VECNUM_MS (32 + 1) /* MAL SERR */ |
| 91 | #define VECNUM_TXDE (32 + 2) /* MAL TXDE */ |
| 92 | #define VECNUM_RXDE (32 + 3) /* MAL RXDE */ |
| 93 | #define VECNUM_MTE (32 + 6) /* MAL Tx EOB */ |
| 94 | #define VECNUM_MRE (32 + 7) /* MAL Rx EOB */ |
| 95 | #define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */ |
| 96 | #define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */ |
| 97 | #define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */ |
| 98 | #define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */ |
| 99 | #define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */ |
| 100 | #define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ |
| 101 | #define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ |
| 102 | |
| 103 | #elif defined(CONFIG_440) |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 104 | |
| 105 | /* UIC 0 */ |
| 106 | #define VECNUM_U0 0 /* UART0 */ |
| 107 | #define VECNUM_U1 1 /* UART1 */ |
| 108 | #define VECNUM_IIC0 2 /* IIC0 */ |
| 109 | #define VECNUM_IIC1 3 /* IIC1 */ |
| 110 | #define VECNUM_PIM 4 /* PCI inbound message */ |
| 111 | #define VECNUM_PCRW 5 /* PCI command reg write */ |
| 112 | #define VECNUM_PPM 6 /* PCI power management */ |
| 113 | #define VECNUM_MSI0 7 /* PCI MSI level 0 */ |
| 114 | #define VECNUM_MSI1 8 /* PCI MSI level 0 */ |
| 115 | #define VECNUM_MSI2 9 /* PCI MSI level 0 */ |
| 116 | #define VECNUM_MTE 10 /* MAL TXEOB */ |
| 117 | #define VECNUM_MRE 11 /* MAL RXEOB */ |
| 118 | #define VECNUM_D0 12 /* DMA channel 0 */ |
| 119 | #define VECNUM_D1 13 /* DMA channel 1 */ |
| 120 | #define VECNUM_D2 14 /* DMA channel 2 */ |
| 121 | #define VECNUM_D3 15 /* DMA channel 3 */ |
| 122 | #define VECNUM_CT0 18 /* GPT compare timer 0 */ |
| 123 | #define VECNUM_CT1 19 /* GPT compare timer 1 */ |
| 124 | #define VECNUM_CT2 20 /* GPT compare timer 2 */ |
| 125 | #define VECNUM_CT3 21 /* GPT compare timer 3 */ |
| 126 | #define VECNUM_CT4 22 /* GPT compare timer 4 */ |
| 127 | #define VECNUM_EIR0 23 /* External interrupt 0 */ |
| 128 | #define VECNUM_EIR1 24 /* External interrupt 1 */ |
| 129 | #define VECNUM_EIR2 25 /* External interrupt 2 */ |
| 130 | #define VECNUM_EIR3 26 /* External interrupt 3 */ |
| 131 | #define VECNUM_EIR4 27 /* External interrupt 4 */ |
| 132 | #define VECNUM_EIR5 28 /* External interrupt 5 */ |
| 133 | #define VECNUM_EIR6 29 /* External interrupt 6 */ |
| 134 | #define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ |
| 135 | #define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ |
| 136 | |
| 137 | /* UIC 1 */ |
| 138 | #define VECNUM_MS (32 + 0 ) /* MAL SERR */ |
| 139 | #define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */ |
| 140 | #define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */ |
| Stefan Roese | 326c971 | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 141 | #define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */ |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 142 | #define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */ |
| 143 | #define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ |
| 144 | |
| 145 | #else /* !defined(CONFIG_440) */ |
| 146 | |
| 147 | #define VECNUM_U0 0 /* UART0 */ |
| 148 | #define VECNUM_U1 1 /* UART1 */ |
| 149 | #define VECNUM_D0 5 /* DMA channel 0 */ |
| 150 | #define VECNUM_D1 6 /* DMA channel 1 */ |
| 151 | #define VECNUM_D2 7 /* DMA channel 2 */ |
| 152 | #define VECNUM_D3 8 /* DMA channel 3 */ |
| 153 | #define VECNUM_EWU0 9 /* Ethernet wakeup */ |
| 154 | #define VECNUM_MS 10 /* MAL SERR */ |
| 155 | #define VECNUM_MTE 11 /* MAL TXEOB */ |
| 156 | #define VECNUM_MRE 12 /* MAL RXEOB */ |
| 157 | #define VECNUM_TXDE 13 /* MAL TXDE */ |
| 158 | #define VECNUM_RXDE 14 /* MAL RXDE */ |
| 159 | #define VECNUM_ETH0 15 /* Ethernet interrupt status */ |
| 160 | #define VECNUM_EIR0 25 /* External interrupt 0 */ |
| 161 | #define VECNUM_EIR1 26 /* External interrupt 1 */ |
| 162 | #define VECNUM_EIR2 27 /* External interrupt 2 */ |
| 163 | #define VECNUM_EIR3 28 /* External interrupt 3 */ |
| 164 | #define VECNUM_EIR4 29 /* External interrupt 4 */ |
| 165 | #define VECNUM_EIR5 30 /* External interrupt 5 */ |
| 166 | #define VECNUM_EIR6 31 /* External interrupt 6 */ |
| 167 | |
| 168 | #endif /* defined(CONFIG_440) */ |
| 169 | |
| 170 | #endif /* _VECNUMS_H_ */ |