Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <clk.h> |
| 8 | #include <dm.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 9 | #include <malloc.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 10 | #include <asm/global_data.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 11 | #include <dm/device_compat.h> |
Marek Vasut | f071c0a | 2019-04-21 22:46:25 +0200 | [diff] [blame] | 12 | #include <dm/pinctrl.h> |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 13 | #include <errno.h> |
| 14 | #include <asm/gpio.h> |
| 15 | #include <asm/io.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 16 | #include <linux/bitops.h> |
Marek Vasut | f22c40a | 2017-11-26 18:08:53 +0100 | [diff] [blame] | 17 | #include "../pinctrl/renesas/sh_pfc.h" |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 18 | |
| 19 | #define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ |
| 20 | #define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */ |
| 21 | #define GPIO_OUTDT 0x08 /* General Output Register */ |
| 22 | #define GPIO_INDT 0x0c /* General Input Register */ |
| 23 | #define GPIO_INTDT 0x10 /* Interrupt Display Register */ |
| 24 | #define GPIO_INTCLR 0x14 /* Interrupt Clear Register */ |
| 25 | #define GPIO_INTMSK 0x18 /* Interrupt Mask Register */ |
| 26 | #define GPIO_MSKCLR 0x1c /* Interrupt Mask Clear Register */ |
| 27 | #define GPIO_POSNEG 0x20 /* Positive/Negative Logic Select Register */ |
| 28 | #define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */ |
| 29 | #define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */ |
| 30 | #define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ |
Marek Vasut | d9544f8 | 2021-04-27 21:29:50 +0200 | [diff] [blame] | 31 | #define GPIO_INEN 0x50 /* General Input Enable Register */ |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 32 | |
| 33 | #define RCAR_MAX_GPIO_PER_BANK 32 |
| 34 | |
Marek Vasut | d9544f8 | 2021-04-27 21:29:50 +0200 | [diff] [blame] | 35 | #define RCAR_GPIO_HAS_INEN BIT(0) |
| 36 | |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 37 | DECLARE_GLOBAL_DATA_PTR; |
| 38 | |
| 39 | struct rcar_gpio_priv { |
Marek Vasut | f22c40a | 2017-11-26 18:08:53 +0100 | [diff] [blame] | 40 | void __iomem *regs; |
Marek Vasut | d9544f8 | 2021-04-27 21:29:50 +0200 | [diff] [blame] | 41 | u32 quirks; |
Marek Vasut | f22c40a | 2017-11-26 18:08:53 +0100 | [diff] [blame] | 42 | int pfc_offset; |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 43 | }; |
| 44 | |
| 45 | static int rcar_gpio_get_value(struct udevice *dev, unsigned offset) |
| 46 | { |
| 47 | struct rcar_gpio_priv *priv = dev_get_priv(dev); |
| 48 | const u32 bit = BIT(offset); |
| 49 | |
| 50 | /* |
| 51 | * Testing on r8a7790 shows that INDT does not show correct pin state |
| 52 | * when configured as output, so use OUTDT in case of output pins. |
| 53 | */ |
| 54 | if (readl(priv->regs + GPIO_INOUTSEL) & bit) |
| 55 | return !!(readl(priv->regs + GPIO_OUTDT) & bit); |
| 56 | else |
| 57 | return !!(readl(priv->regs + GPIO_INDT) & bit); |
| 58 | } |
| 59 | |
| 60 | static int rcar_gpio_set_value(struct udevice *dev, unsigned offset, |
| 61 | int value) |
| 62 | { |
| 63 | struct rcar_gpio_priv *priv = dev_get_priv(dev); |
| 64 | |
| 65 | if (value) |
| 66 | setbits_le32(priv->regs + GPIO_OUTDT, BIT(offset)); |
| 67 | else |
| 68 | clrbits_le32(priv->regs + GPIO_OUTDT, BIT(offset)); |
| 69 | |
| 70 | return 0; |
| 71 | } |
| 72 | |
Marek Vasut | a313601 | 2021-04-27 21:17:43 +0200 | [diff] [blame] | 73 | static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset, |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 74 | bool output) |
| 75 | { |
Marek Vasut | a313601 | 2021-04-27 21:17:43 +0200 | [diff] [blame] | 76 | struct rcar_gpio_priv *priv = dev_get_priv(dev); |
| 77 | void __iomem *regs = priv->regs; |
| 78 | |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 79 | /* |
| 80 | * follow steps in the GPIO documentation for |
| 81 | * "Setting General Output Mode" and |
| 82 | * "Setting General Input Mode" |
| 83 | */ |
| 84 | |
| 85 | /* Configure postive logic in POSNEG */ |
| 86 | clrbits_le32(regs + GPIO_POSNEG, BIT(offset)); |
| 87 | |
Marek Vasut | d9544f8 | 2021-04-27 21:29:50 +0200 | [diff] [blame] | 88 | /* Select "Input Enable/Disable" in INEN */ |
| 89 | if (priv->quirks & RCAR_GPIO_HAS_INEN) { |
| 90 | if (output) |
| 91 | clrbits_le32(regs + GPIO_INEN, BIT(offset)); |
| 92 | else |
| 93 | setbits_le32(regs + GPIO_INEN, BIT(offset)); |
| 94 | } |
| 95 | |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 96 | /* Select "General Input/Output Mode" in IOINTSEL */ |
| 97 | clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset)); |
| 98 | |
| 99 | /* Select Input Mode or Output Mode in INOUTSEL */ |
| 100 | if (output) |
| 101 | setbits_le32(regs + GPIO_INOUTSEL, BIT(offset)); |
| 102 | else |
| 103 | clrbits_le32(regs + GPIO_INOUTSEL, BIT(offset)); |
| 104 | } |
| 105 | |
| 106 | static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset) |
| 107 | { |
Marek Vasut | a313601 | 2021-04-27 21:17:43 +0200 | [diff] [blame] | 108 | rcar_gpio_set_direction(dev, offset, false); |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 109 | |
| 110 | return 0; |
| 111 | } |
| 112 | |
| 113 | static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset, |
| 114 | int value) |
| 115 | { |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 116 | /* write GPIO value to output before selecting output mode of pin */ |
| 117 | rcar_gpio_set_value(dev, offset, value); |
Marek Vasut | a313601 | 2021-04-27 21:17:43 +0200 | [diff] [blame] | 118 | rcar_gpio_set_direction(dev, offset, true); |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 119 | |
| 120 | return 0; |
| 121 | } |
| 122 | |
| 123 | static int rcar_gpio_get_function(struct udevice *dev, unsigned offset) |
| 124 | { |
| 125 | struct rcar_gpio_priv *priv = dev_get_priv(dev); |
| 126 | |
| 127 | if (readl(priv->regs + GPIO_INOUTSEL) & BIT(offset)) |
| 128 | return GPIOF_OUTPUT; |
| 129 | else |
| 130 | return GPIOF_INPUT; |
| 131 | } |
| 132 | |
| 133 | static const struct dm_gpio_ops rcar_gpio_ops = { |
Pali Rohár | 6916dc2 | 2022-08-02 12:06:55 +0200 | [diff] [blame] | 134 | .request = pinctrl_gpio_request, |
| 135 | .rfree = pinctrl_gpio_free, |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 136 | .direction_input = rcar_gpio_direction_input, |
| 137 | .direction_output = rcar_gpio_direction_output, |
| 138 | .get_value = rcar_gpio_get_value, |
| 139 | .set_value = rcar_gpio_set_value, |
| 140 | .get_function = rcar_gpio_get_function, |
| 141 | }; |
| 142 | |
| 143 | static int rcar_gpio_probe(struct udevice *dev) |
| 144 | { |
| 145 | struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
| 146 | struct rcar_gpio_priv *priv = dev_get_priv(dev); |
| 147 | struct fdtdec_phandle_args args; |
| 148 | struct clk clk; |
| 149 | int node = dev_of_offset(dev); |
| 150 | int ret; |
| 151 | |
Masahiro Yamada | 1096ae1 | 2020-07-17 14:36:46 +0900 | [diff] [blame] | 152 | priv->regs = dev_read_addr_ptr(dev); |
Marek Vasut | d9544f8 | 2021-04-27 21:29:50 +0200 | [diff] [blame] | 153 | priv->quirks = dev_get_driver_data(dev); |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 154 | uc_priv->bank_name = dev->name; |
| 155 | |
| 156 | ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges", |
| 157 | NULL, 3, 0, &args); |
Marek Vasut | f22c40a | 2017-11-26 18:08:53 +0100 | [diff] [blame] | 158 | priv->pfc_offset = ret == 0 ? args.args[1] : -1; |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 159 | uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK; |
| 160 | |
| 161 | ret = clk_get_by_index(dev, 0, &clk); |
| 162 | if (ret < 0) { |
| 163 | dev_err(dev, "Failed to get GPIO bank clock\n"); |
| 164 | return ret; |
| 165 | } |
| 166 | |
| 167 | ret = clk_enable(&clk); |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 168 | if (ret) { |
| 169 | dev_err(dev, "Failed to enable GPIO bank clock\n"); |
| 170 | return ret; |
| 171 | } |
| 172 | |
| 173 | return 0; |
| 174 | } |
| 175 | |
| 176 | static const struct udevice_id rcar_gpio_ids[] = { |
| 177 | { .compatible = "renesas,gpio-r8a7795" }, |
| 178 | { .compatible = "renesas,gpio-r8a7796" }, |
Marek Vasut | 87f22c2 | 2018-02-26 10:35:15 +0100 | [diff] [blame] | 179 | { .compatible = "renesas,gpio-r8a77965" }, |
Marek Vasut | 6403ab8 | 2017-10-21 11:27:04 +0200 | [diff] [blame] | 180 | { .compatible = "renesas,gpio-r8a77970" }, |
Marek Vasut | ca4b4eb | 2018-04-26 13:18:45 +0200 | [diff] [blame] | 181 | { .compatible = "renesas,gpio-r8a77990" }, |
Marek Vasut | c129f2b | 2017-10-21 11:28:06 +0200 | [diff] [blame] | 182 | { .compatible = "renesas,gpio-r8a77995" }, |
Marek Vasut | d9544f8 | 2021-04-27 21:29:50 +0200 | [diff] [blame] | 183 | { .compatible = "renesas,gpio-r8a779a0", .data = RCAR_GPIO_HAS_INEN }, |
Marek Vasut | e4f6e9b | 2018-01-18 00:52:15 +0100 | [diff] [blame] | 184 | { .compatible = "renesas,rcar-gen2-gpio" }, |
Marek Vasut | 54a34ed | 2017-10-21 11:30:41 +0200 | [diff] [blame] | 185 | { .compatible = "renesas,rcar-gen3-gpio" }, |
Hai Pham | 2120b5c | 2023-02-28 22:23:07 +0100 | [diff] [blame] | 186 | { .compatible = "renesas,rcar-gen4-gpio", .data = RCAR_GPIO_HAS_INEN }, |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 187 | { /* sentinel */ } |
| 188 | }; |
| 189 | |
| 190 | U_BOOT_DRIVER(rcar_gpio) = { |
| 191 | .name = "rcar-gpio", |
| 192 | .id = UCLASS_GPIO, |
| 193 | .of_match = rcar_gpio_ids, |
| 194 | .ops = &rcar_gpio_ops, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 195 | .priv_auto = sizeof(struct rcar_gpio_priv), |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 196 | .probe = rcar_gpio_probe, |
| 197 | }; |