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git01.mediatek.com / filogic / uboot / 497c51669c351d7ef928b0a2c273207c8935c0a5 / . / doc / device-tree-bindings / misc / intel,baytrail-fsp.txt
blob: 691ae53b65cf08f37b5d82643a37c023784cb3fc [file] [log] [blame]
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]1Intel Bay Trail FSP UPD Binding
2===============================
3
4The device tree node which describes the overriding of the Intel Bay Trail FSP
5UPD data for configuring the SoC.
6
7All properties can be found within the `upd-region` struct in
8arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in
Bin Meng497c5162017-05-31 01:04:14 -0700[diff] [blame^]9Intel's FSP Binary Configuration Tool for Bay Trail. This list of properties
10is matched up to Intel's E3800 FSPv4 release.
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]11
12# Boolean properties:
13
14- fsp,enable-sdio
15- fsp,enable-sdcard
16- fsp,enable-hsuart0
17- fsp,enable-hsuart1
18- fsp,enable-spi
19- fsp,enable-sata
20- fsp,enable-azalia
21- fsp,enable-xhci
22- fsp,enable-lpe
23- fsp,lpss-sio-enable-pci-mode
24- fsp,enable-dma0
25- fsp,enable-dma1
26- fsp,enable-i2-c0
27- fsp,enable-i2-c1
28- fsp,enable-i2-c2
29- fsp,enable-i2-c3
30- fsp,enable-i2-c4
31- fsp,enable-i2-c5
32- fsp,enable-i2-c6
33- fsp,enable-pwm0
34- fsp,enable-pwm1
35- fsp,enable-hsi
36- fsp,mrc-debug-msg
37- fsp,isp-enable
38- fsp,scc-enable-pci-mode
39- fsp,igd-render-standby
40- fsp,txe-uma-enable
41- fsp,emmc45-ddr50-enabled
42- fsp,emmc45-hs200-enabled
43- fsp,enable-igd
44- fsp,enable-memory-down
45
46If you set "fsp,enable-memory-down" you are strongly encouraged to provide an
Bin Meng497c5162017-05-31 01:04:14 -0700[diff] [blame^]47"fsp,memory-down-params{};" to specify how your memory is configured. If you
48do not set "fsp,enable-memory-down", then the DIMM SPD information will be
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]49discovered by the FSP and used to setup main memory.
50
51
52# Integer properties:
53
54- fsp,mrc-init-tseg-size
55- fsp,mrc-init-mmio-size
56- fsp,mrc-init-spd-addr1
57- fsp,mrc-init-spd-addr2
58- fsp,emmc-boot-mode
59- fsp,sata-mode
60- fsp,igd-dvmt50-pre-alloc
61- fsp,aperture-size
62- fsp,gtt-size
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]63- fsp,os-selection
64- fsp,emmc45-retune-timer-value
65
66- fsp,memory-down-params {
67
68 # Boolean properties:
69
70 - fsp,dimm-0-enable
71 - fsp,dimm-1-enable
72
73 # Integer properties:
74
Bin Meng497c5162017-05-31 01:04:14 -0700[diff] [blame^]75 - fsp,dram-speed
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]76 - fsp,dram-type
77 - fsp,dimm-width
78 - fsp,dimm-density
79 - fsp,dimm-bus-width
80 - fsp,dimm-sides
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]81 - fsp,dimm-tcl
82 - fsp,dimm-trpt-rcd
83 - fsp,dimm-twr
84 - fsp,dimm-twtr
85 - fsp,dimm-trrd
86 - fsp,dimm-trtp
87 - fsp,dimm-tfaw
88};
89
Bin Meng497c5162017-05-31 01:04:14 -0700[diff] [blame^]90For all integer properties, available options are listed in fsp_configs.h in
91arch/x86/include/asm/arch-baytrail/fsp directory (eg: MRC_INIT_TSEG_SIZE_1MB).
92
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]93
94Example (from MinnowMax Dual Core):
95-----------------------------------
96
97/ {
98 ...
99
100 fsp {
101 compatible = "intel,baytrail-fsp";
Bin Meng497c5162017-05-31 01:04:14 -0700[diff] [blame^]102 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
103 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]104 fsp,mrc-init-spd-addr1 = <0xa0>;
105 fsp,mrc-init-spd-addr2 = <0xa2>;
Bin Meng497c5162017-05-31 01:04:14 -0700[diff] [blame^]106 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]107 fsp,enable-sdio;
108 fsp,enable-sdcard;
109 fsp,enable-hsuart1;
110 fsp,enable-spi;
111 fsp,enable-sata;
Bin Meng497c5162017-05-31 01:04:14 -0700[diff] [blame^]112 fsp,sata-mode = <SATA_MODE_AHCI>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]113 fsp,enable-lpe;
114 fsp,lpss-sio-enable-pci-mode;
115 fsp,enable-dma0;
116 fsp,enable-dma1;
117 fsp,enable-i2c0;
118 fsp,enable-i2c1;
119 fsp,enable-i2c2;
120 fsp,enable-i2c3;
121 fsp,enable-i2c4;
122 fsp,enable-i2c5;
123 fsp,enable-i2c6;
124 fsp,enable-pwm0;
125 fsp,enable-pwm1;
Bin Meng497c5162017-05-31 01:04:14 -0700[diff] [blame^]126 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
127 fsp,aperture-size = <APERTURE_SIZE_256MB>;
128 fsp,gtt-size = <GTT_SIZE_2MB>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]129 fsp,scc-enable-pci-mode;
Bin Meng497c5162017-05-31 01:04:14 -0700[diff] [blame^]130 fsp,os-selection = <OS_SELECTION_LINUX>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]131 fsp,emmc45-ddr50-enabled;
132 fsp,emmc45-retune-timer-value = <8>;
133 fsp,enable-igd;
134 fsp,enable-memory-down;
135 fsp,memory-down-params {
136 compatible = "intel,baytrail-fsp-mdp";
Bin Meng497c5162017-05-31 01:04:14 -0700[diff] [blame^]137 fsp,dram-speed = <DRAM_SPEED_1066MTS>;
138 fsp,dram-type = <DRAM_TYPE_DDR3L>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]139 fsp,dimm-0-enable;
Bin Meng497c5162017-05-31 01:04:14 -0700[diff] [blame^]140 fsp,dimm-width = <DIMM_WIDTH_X16>;
141 fsp,dimm-density = <DIMM_DENSITY_4GBIT>;
142 fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
143 fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400[diff] [blame]144 fsp,dimm-tcl = <0xb>;
145 fsp,dimm-trpt-rcd = <0xb>;
146 fsp,dimm-twr = <0xc>;
147 fsp,dimm-twtr = <6>;
148 fsp,dimm-trrd = <6>;
149 fsp,dimm-trtp = <6>;
150 fsp,dimm-tfaw = <0x14>;
151 };
152 };
153
154 ...
155};