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Suman Anna3b431102022-05-25 13:38:47 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Board specific initialization for AM62x platforms
4 *
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
7 *
8 */
9
Nikhil M Jain155a0822023-01-31 15:35:19 +053010#include <env.h>
Suman Anna3b431102022-05-25 13:38:47 +053011#include <spl.h>
Nikhil M Jain155a0822023-01-31 15:35:19 +053012#include <video.h>
13#include <splash.h>
Georgi Vlaev18c0fbf2022-06-14 17:45:33 +030014#include <k3-ddrss.h>
Suman Anna3b431102022-05-25 13:38:47 +053015#include <fdt_support.h>
Nikhil M Jain155a0822023-01-31 15:35:19 +053016#include <asm/io.h>
Suman Anna3b431102022-05-25 13:38:47 +053017#include <asm/arch/hardware.h>
Nikhil M Jain155a0822023-01-31 15:35:19 +053018#include <dm/uclass.h>
Suman Anna3b431102022-05-25 13:38:47 +053019
20DECLARE_GLOBAL_DATA_PTR;
21
Nikhil M Jain1ff64a22023-04-20 17:41:11 +053022#if CONFIG_IS_ENABLED(SPLASH_SCREEN)
Nikhil M Jain155a0822023-01-31 15:35:19 +053023static struct splash_location default_splash_locations[] = {
24 {
Nikhil M Jain1ff64a22023-04-20 17:41:11 +053025 .name = "sf",
26 .storage = SPLASH_STORAGE_SF,
27 .flags = SPLASH_STORAGE_RAW,
28 .offset = 0x700000,
29 },
30 {
Nikhil M Jain155a0822023-01-31 15:35:19 +053031 .name = "mmc",
32 .storage = SPLASH_STORAGE_MMC,
33 .flags = SPLASH_STORAGE_FS,
34 .devpart = "1:1",
35 },
36};
37
38int splash_screen_prepare(void)
39{
40 return splash_source_load(default_splash_locations,
41 ARRAY_SIZE(default_splash_locations));
42}
43#endif
44
Suman Anna3b431102022-05-25 13:38:47 +053045int board_init(void)
46{
47 return 0;
48}
49
50int dram_init(void)
51{
Georgi Vlaev8a9ceb42022-06-14 17:45:32 +030052 return fdtdec_setup_mem_size_base();
Suman Anna3b431102022-05-25 13:38:47 +053053}
54
55int dram_init_banksize(void)
56{
Georgi Vlaev8a9ceb42022-06-14 17:45:32 +030057 return fdtdec_setup_memory_banksize();
Suman Anna3b431102022-05-25 13:38:47 +053058}
Georgi Vlaev18c0fbf2022-06-14 17:45:33 +030059
60#if defined(CONFIG_SPL_BUILD)
61#if defined(CONFIG_K3_AM64_DDRSS)
62static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
63{
64 struct udevice *dev;
65 int ret;
66
67 dram_init_banksize();
68
69 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
70 if (ret)
71 panic("Cannot get RAM device for ddr size fixup: %d\n", ret);
72
73 ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
74 if (ret)
75 printf("Error fixing up ddr node for ECC use! %d\n", ret);
76}
77#else
78static void fixup_memory_node(struct spl_image_info *spl_image)
79{
80 u64 start[CONFIG_NR_DRAM_BANKS];
81 u64 size[CONFIG_NR_DRAM_BANKS];
82 int bank;
83 int ret;
84
85 dram_init();
86 dram_init_banksize();
87
88 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
89 start[bank] = gd->bd->bi_dram[bank].start;
90 size[bank] = gd->bd->bi_dram[bank].size;
91 }
92
93 /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */
94 ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
95 CONFIG_NR_DRAM_BANKS);
96 if (ret)
97 printf("Error fixing up memory node! %d\n", ret);
98}
99#endif
100
101void spl_perform_fixups(struct spl_image_info *spl_image)
102{
103#if defined(CONFIG_K3_AM64_DDRSS)
104 fixup_ddr_driver_for_ecc(spl_image);
105#else
106 fixup_memory_node(spl_image);
107#endif
108}
109#endif