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wdenkbb1b8262003-03-27 12:09:35 +00001/*
wdenk8d5d28a2005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
wdenkbb1b8262003-03-27 12:09:35 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * This file contains the configuration parameters for the INCA-IP board.
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
32#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
33
wdenk5d841732003-08-17 18:55:18 +000034#ifndef CPU_CLOCK_RATE
wdenk92bbe3f2003-04-20 14:04:18 +000035/* allowed values: 100000000, 133000000, and 150000000 */
wdenk41d153a2004-01-06 11:32:21 +000036#define CPU_CLOCK_RATE 150000000 /* default: 150 MHz clock for the MIPS core */
wdenk5d841732003-08-17 18:55:18 +000037#endif
wdenkbb1b8262003-03-27 12:09:35 +000038
wdenk67f13362003-12-27 19:24:54 +000039#define INFINEON_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */
wdenkbb1b8262003-03-27 12:09:35 +000040
wdenkb02744a2003-04-05 00:53:31 +000041#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkbb1b8262003-03-27 12:09:35 +000042
wdenkb02744a2003-04-05 00:53:31 +000043#define CONFIG_BAUDRATE 115200
wdenkbb1b8262003-03-27 12:09:35 +000044
45/* valid baudrates */
46#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
47
wdenkb02744a2003-04-05 00:53:31 +000048#define CONFIG_TIMESTAMP /* Print image info with timestamp */
49
50#define CONFIG_PREBOOT "echo;" \
51 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
52 "echo"
53
54#undef CONFIG_BOOTARGS
55
56#define CONFIG_EXTRA_ENV_SETTINGS \
57 "nfsargs=setenv bootargs root=/dev/nfs rw " \
58 "nfsroot=$(serverip):$(rootpath)\0" \
59 "ramargs=setenv bootargs root=/dev/ram rw\0" \
60 "addip=setenv bootargs $(bootargs) " \
61 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
62 ":$(hostname):$(netdev):off\0" \
63 "addmisc=setenv bootargs $(bootargs) " \
64 "console=ttyS0,$(baudrate) " \
65 "ethaddr=$(ethaddr) " \
66 "panic=1\0" \
67 "flash_nfs=run nfsargs addip addmisc;" \
68 "bootm $(kernel_addr)\0" \
69 "flash_self=run ramargs addip addmisc;" \
70 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
71 "net_nfs=tftp 80500000 $(bootfile);" \
72 "run nfsargs addip addmisc;bootm\0" \
73 "rootpath=/opt/eldk/mips_4KC\0" \
74 "bootfile=/tftpboot/INCA/uImage\0" \
75 "kernel_addr=B0040000\0" \
76 "ramdisk_addr=B0100000\0" \
77 "u-boot=/tftpboot/INCA/u-boot.bin\0" \
78 "load=tftp 80500000 $(u-boot)\0" \
79 "update=protect off 1:0-2;era 1:0-2;" \
80 "cp.b 80500000 B0000000 $(filesize)\0" \
81 ""
82#define CONFIG_BOOTCOMMAND "run flash_self"
83
wdenk8d5d28a2005-04-02 22:37:54 +000084#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
85 CFG_CMD_ASKENV | \
86 CFG_CMD_DHCP | \
87 CFG_CMD_ELF | \
88 CFG_CMD_JFFS2 | \
89 CFG_CMD_NFS | \
90 CFG_CMD_PING | \
91 CFG_CMD_SNTP )
wdenkbb1b8262003-03-27 12:09:35 +000092#include <cmd_confdefs.h>
93
94/*
95 * Miscellaneous configurable options
96 */
97#define CFG_LONGHELP /* undef to save memory */
98#define CFG_PROMPT "INCA-IP # " /* Monitor Command Prompt */
99#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
100#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
wdenkbb1b8262003-03-27 12:09:35 +0000101#define CFG_MAXARGS 16 /* max number of command args*/
102
wdenkb02744a2003-04-05 00:53:31 +0000103#define CFG_MALLOC_LEN 128*1024
104
105#define CFG_BOOTPARAMS_LEN 128*1024
106
wdenk67f13362003-12-27 19:24:54 +0000107#define CFG_HZ (incaip_get_cpuclk() / 2)
wdenkb02744a2003-04-05 00:53:31 +0000108
109#define CFG_SDRAM_BASE 0x80000000
110
wdenkbb1b8262003-03-27 12:09:35 +0000111#define CFG_LOAD_ADDR 0x80100000 /* default load address */
112
wdenkb02744a2003-04-05 00:53:31 +0000113#define CFG_MEMTEST_START 0x80100000
wdenkbb1b8262003-03-27 12:09:35 +0000114#define CFG_MEMTEST_END 0x80800000
115
116/*-----------------------------------------------------------------------
117 * FLASH and environment organization
118 */
119#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
120#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
121
122#define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */
123#define PHYS_FLASH_2 0xb0800000 /* Flash Bank #2 */
124
125/* The following #defines are needed to get flash environment right */
126#define CFG_MONITOR_BASE TEXT_BASE
127#define CFG_MONITOR_LEN (192 << 10)
128
129#define CFG_INIT_SP_OFFSET 0x400000
130
131#define CFG_FLASH_BASE PHYS_FLASH_1
132
133/* timeout values are in ticks */
134#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
135#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
136
137#define CFG_ENV_IS_IN_FLASH 1
138
139/* Address and size of Primary Environment Sector */
140#define CFG_ENV_ADDR 0xB0030000
141#define CFG_ENV_SIZE 0x10000
142
143#define CONFIG_FLASH_16BIT
144
145#define CONFIG_NR_DRAM_BANKS 1
146
147#define CONFIG_INCA_IP_SWITCH
148#define CONFIG_NET_MULTI
wdenkdb82c8e2004-02-26 23:01:04 +0000149#define CONFIG_INCA_IP_SWITCH_AMDIX
wdenkbb1b8262003-03-27 12:09:35 +0000150
wdenkdf28aa02003-12-12 00:02:26 +0000151#define CFG_JFFS2_FIRST_BANK 1
152#define CFG_JFFS2_NUM_BANKS 1
153
wdenkbb1b8262003-03-27 12:09:35 +0000154/*-----------------------------------------------------------------------
155 * Cache Configuration
156 */
157#define CFG_DCACHE_SIZE 4096
158#define CFG_ICACHE_SIZE 4096
159#define CFG_CACHELINE_SIZE 16
160
161#endif /* __CONFIG_H */