Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2014 Google, Inc |
| 4 | * |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 5 | * Memory Type Range Regsters - these are used to tell the CPU whether |
| 6 | * memory is cacheable and if so the cache write mode to use. |
| 7 | * |
| 8 | * These can speed up booting. See the mtrr command. |
| 9 | * |
| 10 | * Reference: Intel Architecture Software Developer's Manual, Volume 3: |
| 11 | * System Programming |
| 12 | */ |
| 13 | |
Simon Glass | 8fafd01 | 2018-10-01 12:22:37 -0600 | [diff] [blame] | 14 | /* |
| 15 | * Note that any console output (e.g. debug()) in this file will likely fail |
| 16 | * since the MTRR registers are sometimes in flux. |
| 17 | */ |
| 18 | |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 19 | #include <common.h> |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 20 | #include <cpu_func.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 21 | #include <log.h> |
Simon Glass | 6b88e88 | 2020-09-22 12:45:27 -0600 | [diff] [blame] | 22 | #include <sort.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 23 | #include <asm/cache.h> |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 24 | #include <asm/io.h> |
Simon Glass | 7403c26 | 2020-07-17 08:48:22 -0600 | [diff] [blame] | 25 | #include <asm/mp.h> |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 26 | #include <asm/msr.h> |
| 27 | #include <asm/mtrr.h> |
| 28 | |
Bin Meng | 068fb35 | 2015-01-22 11:29:39 +0800 | [diff] [blame] | 29 | DECLARE_GLOBAL_DATA_PTR; |
| 30 | |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 31 | /* Prepare to adjust MTRRs */ |
Simon Glass | 8fafd01 | 2018-10-01 12:22:37 -0600 | [diff] [blame] | 32 | void mtrr_open(struct mtrr_state *state, bool do_caches) |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 33 | { |
Bin Meng | 80d2976 | 2015-01-22 11:29:41 +0800 | [diff] [blame] | 34 | if (!gd->arch.has_mtrr) |
| 35 | return; |
| 36 | |
Simon Glass | 8fafd01 | 2018-10-01 12:22:37 -0600 | [diff] [blame] | 37 | if (do_caches) { |
| 38 | state->enable_cache = dcache_status(); |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 39 | |
Simon Glass | 8fafd01 | 2018-10-01 12:22:37 -0600 | [diff] [blame] | 40 | if (state->enable_cache) |
| 41 | disable_caches(); |
| 42 | } |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 43 | state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR); |
| 44 | wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN); |
| 45 | } |
| 46 | |
| 47 | /* Clean up after adjusting MTRRs, and enable them */ |
Simon Glass | 8fafd01 | 2018-10-01 12:22:37 -0600 | [diff] [blame] | 48 | void mtrr_close(struct mtrr_state *state, bool do_caches) |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 49 | { |
Bin Meng | 80d2976 | 2015-01-22 11:29:41 +0800 | [diff] [blame] | 50 | if (!gd->arch.has_mtrr) |
| 51 | return; |
| 52 | |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 53 | wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN); |
Simon Glass | 8fafd01 | 2018-10-01 12:22:37 -0600 | [diff] [blame] | 54 | if (do_caches && state->enable_cache) |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 55 | enable_caches(); |
| 56 | } |
| 57 | |
Simon Glass | 3552059 | 2019-09-25 08:56:45 -0600 | [diff] [blame] | 58 | static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size) |
| 59 | { |
| 60 | u64 mask; |
| 61 | |
| 62 | wrmsrl(MTRR_PHYS_BASE_MSR(reg), start | type); |
| 63 | mask = ~(size - 1); |
| 64 | mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; |
| 65 | wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID); |
| 66 | } |
| 67 | |
Simon Glass | 7403c26 | 2020-07-17 08:48:22 -0600 | [diff] [blame] | 68 | void mtrr_read_all(struct mtrr_info *info) |
| 69 | { |
Simon Glass | fbf120c | 2020-09-22 14:54:51 -0600 | [diff] [blame] | 70 | int reg_count = mtrr_get_var_count(); |
Simon Glass | 7403c26 | 2020-07-17 08:48:22 -0600 | [diff] [blame] | 71 | int i; |
| 72 | |
Simon Glass | fbf120c | 2020-09-22 14:54:51 -0600 | [diff] [blame] | 73 | for (i = 0; i < reg_count; i++) { |
Simon Glass | 7403c26 | 2020-07-17 08:48:22 -0600 | [diff] [blame] | 74 | info->mtrr[i].base = native_read_msr(MTRR_PHYS_BASE_MSR(i)); |
| 75 | info->mtrr[i].mask = native_read_msr(MTRR_PHYS_MASK_MSR(i)); |
| 76 | } |
| 77 | } |
| 78 | |
Simon Glass | 00dc52f | 2020-07-17 08:48:25 -0600 | [diff] [blame] | 79 | void mtrr_write_all(struct mtrr_info *info) |
| 80 | { |
Simon Glass | fbf120c | 2020-09-22 14:54:51 -0600 | [diff] [blame] | 81 | int reg_count = mtrr_get_var_count(); |
Simon Glass | 00dc52f | 2020-07-17 08:48:25 -0600 | [diff] [blame] | 82 | struct mtrr_state state; |
| 83 | int i; |
| 84 | |
Simon Glass | fbf120c | 2020-09-22 14:54:51 -0600 | [diff] [blame] | 85 | for (i = 0; i < reg_count; i++) { |
Simon Glass | 00dc52f | 2020-07-17 08:48:25 -0600 | [diff] [blame] | 86 | mtrr_open(&state, true); |
| 87 | wrmsrl(MTRR_PHYS_BASE_MSR(i), info->mtrr[i].base); |
| 88 | wrmsrl(MTRR_PHYS_MASK_MSR(i), info->mtrr[i].mask); |
| 89 | mtrr_close(&state, true); |
| 90 | } |
| 91 | } |
| 92 | |
| 93 | static void write_mtrrs(void *arg) |
| 94 | { |
| 95 | struct mtrr_info *info = arg; |
| 96 | |
| 97 | mtrr_write_all(info); |
| 98 | } |
| 99 | |
| 100 | static void read_mtrrs(void *arg) |
| 101 | { |
| 102 | struct mtrr_info *info = arg; |
| 103 | |
| 104 | mtrr_read_all(info); |
| 105 | } |
| 106 | |
| 107 | /** |
| 108 | * mtrr_copy_to_aps() - Copy the MTRRs from the boot CPU to other CPUs |
| 109 | * |
| 110 | * @return 0 on success, -ve on failure |
| 111 | */ |
| 112 | static int mtrr_copy_to_aps(void) |
| 113 | { |
| 114 | struct mtrr_info info; |
| 115 | int ret; |
| 116 | |
| 117 | ret = mp_run_on_cpus(MP_SELECT_BSP, read_mtrrs, &info); |
| 118 | if (ret == -ENXIO) |
| 119 | return 0; |
| 120 | else if (ret) |
| 121 | return log_msg_ret("bsp", ret); |
| 122 | |
| 123 | ret = mp_run_on_cpus(MP_SELECT_APS, write_mtrrs, &info); |
| 124 | if (ret) |
| 125 | return log_msg_ret("bsp", ret); |
| 126 | |
| 127 | return 0; |
| 128 | } |
| 129 | |
Simon Glass | 6b88e88 | 2020-09-22 12:45:27 -0600 | [diff] [blame] | 130 | static int h_comp_mtrr(const void *p1, const void *p2) |
| 131 | { |
| 132 | const struct mtrr_request *req1 = p1; |
| 133 | const struct mtrr_request *req2 = p2; |
| 134 | |
| 135 | s64 diff = req1->start - req2->start; |
| 136 | |
| 137 | return diff < 0 ? -1 : diff > 0 ? 1 : 0; |
| 138 | } |
| 139 | |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 140 | int mtrr_commit(bool do_caches) |
| 141 | { |
| 142 | struct mtrr_request *req = gd->arch.mtrr_req; |
| 143 | struct mtrr_state state; |
Simon Glass | 00dc52f | 2020-07-17 08:48:25 -0600 | [diff] [blame] | 144 | int ret; |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 145 | int i; |
| 146 | |
Simon Glass | 8fafd01 | 2018-10-01 12:22:37 -0600 | [diff] [blame] | 147 | debug("%s: enabled=%d, count=%d\n", __func__, gd->arch.has_mtrr, |
| 148 | gd->arch.mtrr_req_count); |
Bin Meng | 80d2976 | 2015-01-22 11:29:41 +0800 | [diff] [blame] | 149 | if (!gd->arch.has_mtrr) |
| 150 | return -ENOSYS; |
| 151 | |
Simon Glass | 8fafd01 | 2018-10-01 12:22:37 -0600 | [diff] [blame] | 152 | debug("open\n"); |
| 153 | mtrr_open(&state, do_caches); |
| 154 | debug("open done\n"); |
Simon Glass | 6b88e88 | 2020-09-22 12:45:27 -0600 | [diff] [blame] | 155 | qsort(req, gd->arch.mtrr_req_count, sizeof(*req), h_comp_mtrr); |
Simon Glass | 3552059 | 2019-09-25 08:56:45 -0600 | [diff] [blame] | 156 | for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) |
| 157 | set_var_mtrr(i, req->type, req->start, req->size); |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 158 | |
| 159 | /* Clear the ones that are unused */ |
Simon Glass | 8fafd01 | 2018-10-01 12:22:37 -0600 | [diff] [blame] | 160 | debug("clear\n"); |
Simon Glass | fbf120c | 2020-09-22 14:54:51 -0600 | [diff] [blame] | 161 | for (; i < MTRR_MAX_COUNT; i++) |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 162 | wrmsrl(MTRR_PHYS_MASK_MSR(i), 0); |
Simon Glass | 8fafd01 | 2018-10-01 12:22:37 -0600 | [diff] [blame] | 163 | debug("close\n"); |
| 164 | mtrr_close(&state, do_caches); |
| 165 | debug("mtrr done\n"); |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 166 | |
Simon Glass | 00dc52f | 2020-07-17 08:48:25 -0600 | [diff] [blame] | 167 | if (gd->flags & GD_FLG_RELOC) { |
| 168 | ret = mtrr_copy_to_aps(); |
| 169 | if (ret) |
| 170 | return log_msg_ret("copy", ret); |
| 171 | } |
| 172 | |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 173 | return 0; |
| 174 | } |
| 175 | |
| 176 | int mtrr_add_request(int type, uint64_t start, uint64_t size) |
| 177 | { |
| 178 | struct mtrr_request *req; |
| 179 | uint64_t mask; |
| 180 | |
Simon Glass | 8fafd01 | 2018-10-01 12:22:37 -0600 | [diff] [blame] | 181 | debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count); |
Bin Meng | 80d2976 | 2015-01-22 11:29:41 +0800 | [diff] [blame] | 182 | if (!gd->arch.has_mtrr) |
| 183 | return -ENOSYS; |
| 184 | |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 185 | if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS) |
| 186 | return -ENOSPC; |
| 187 | req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++]; |
| 188 | req->type = type; |
| 189 | req->start = start; |
| 190 | req->size = size; |
| 191 | debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1, |
| 192 | req->type, req->start, req->size); |
| 193 | mask = ~(req->size - 1); |
| 194 | mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; |
| 195 | mask |= MTRR_PHYS_MASK_VALID; |
| 196 | debug(" %016llx %016llx\n", req->start | req->type, mask); |
| 197 | |
| 198 | return 0; |
| 199 | } |
Simon Glass | 753297d | 2019-09-25 08:56:46 -0600 | [diff] [blame] | 200 | |
Simon Glass | fbf120c | 2020-09-22 14:54:51 -0600 | [diff] [blame] | 201 | int mtrr_get_var_count(void) |
Simon Glass | 753297d | 2019-09-25 08:56:46 -0600 | [diff] [blame] | 202 | { |
| 203 | return msr_read(MSR_MTRR_CAP_MSR).lo & MSR_MTRR_CAP_VCNT; |
| 204 | } |
| 205 | |
| 206 | static int get_free_var_mtrr(void) |
| 207 | { |
| 208 | struct msr_t maskm; |
| 209 | int vcnt; |
| 210 | int i; |
| 211 | |
Simon Glass | fbf120c | 2020-09-22 14:54:51 -0600 | [diff] [blame] | 212 | vcnt = mtrr_get_var_count(); |
Simon Glass | 753297d | 2019-09-25 08:56:46 -0600 | [diff] [blame] | 213 | |
| 214 | /* Identify the first var mtrr which is not valid */ |
| 215 | for (i = 0; i < vcnt; i++) { |
| 216 | maskm = msr_read(MTRR_PHYS_MASK_MSR(i)); |
| 217 | if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0) |
| 218 | return i; |
| 219 | } |
| 220 | |
| 221 | /* No free var mtrr */ |
| 222 | return -ENOSPC; |
| 223 | } |
| 224 | |
| 225 | int mtrr_set_next_var(uint type, uint64_t start, uint64_t size) |
| 226 | { |
| 227 | int mtrr; |
| 228 | |
| 229 | mtrr = get_free_var_mtrr(); |
| 230 | if (mtrr < 0) |
| 231 | return mtrr; |
| 232 | |
| 233 | set_var_mtrr(mtrr, type, start, size); |
| 234 | debug("MTRR %x: start=%x, size=%x\n", mtrr, (uint)start, (uint)size); |
| 235 | |
| 236 | return 0; |
| 237 | } |
Simon Glass | d89e15f | 2020-07-17 08:48:26 -0600 | [diff] [blame] | 238 | |
| 239 | /** enum mtrr_opcode - supported operations for mtrr_do_oper() */ |
| 240 | enum mtrr_opcode { |
| 241 | MTRR_OP_SET, |
| 242 | MTRR_OP_SET_VALID, |
| 243 | }; |
| 244 | |
| 245 | /** |
| 246 | * struct mtrr_oper - An MTRR operation to perform on a CPU |
| 247 | * |
| 248 | * @opcode: Indicates operation to perform |
| 249 | * @reg: MTRR reg number to select (0-7, -1 = all) |
| 250 | * @valid: Valid value to write for MTRR_OP_SET_VALID |
| 251 | * @base: Base value to write for MTRR_OP_SET |
| 252 | * @mask: Mask value to write for MTRR_OP_SET |
| 253 | */ |
| 254 | struct mtrr_oper { |
| 255 | enum mtrr_opcode opcode; |
| 256 | int reg; |
| 257 | bool valid; |
| 258 | u64 base; |
| 259 | u64 mask; |
| 260 | }; |
| 261 | |
| 262 | static void mtrr_do_oper(void *arg) |
| 263 | { |
| 264 | struct mtrr_oper *oper = arg; |
| 265 | u64 mask; |
| 266 | |
| 267 | switch (oper->opcode) { |
| 268 | case MTRR_OP_SET_VALID: |
| 269 | mask = native_read_msr(MTRR_PHYS_MASK_MSR(oper->reg)); |
| 270 | if (oper->valid) |
| 271 | mask |= MTRR_PHYS_MASK_VALID; |
| 272 | else |
| 273 | mask &= ~MTRR_PHYS_MASK_VALID; |
| 274 | wrmsrl(MTRR_PHYS_MASK_MSR(oper->reg), mask); |
| 275 | break; |
| 276 | case MTRR_OP_SET: |
| 277 | wrmsrl(MTRR_PHYS_BASE_MSR(oper->reg), oper->base); |
| 278 | wrmsrl(MTRR_PHYS_MASK_MSR(oper->reg), oper->mask); |
| 279 | break; |
| 280 | } |
| 281 | } |
| 282 | |
| 283 | static int mtrr_start_op(int cpu_select, struct mtrr_oper *oper) |
| 284 | { |
| 285 | struct mtrr_state state; |
| 286 | int ret; |
| 287 | |
| 288 | mtrr_open(&state, true); |
| 289 | ret = mp_run_on_cpus(cpu_select, mtrr_do_oper, oper); |
| 290 | mtrr_close(&state, true); |
| 291 | if (ret) |
| 292 | return log_msg_ret("run", ret); |
| 293 | |
| 294 | return 0; |
| 295 | } |
| 296 | |
| 297 | int mtrr_set_valid(int cpu_select, int reg, bool valid) |
| 298 | { |
| 299 | struct mtrr_oper oper; |
| 300 | |
| 301 | oper.opcode = MTRR_OP_SET_VALID; |
| 302 | oper.reg = reg; |
| 303 | oper.valid = valid; |
| 304 | |
| 305 | return mtrr_start_op(cpu_select, &oper); |
| 306 | } |
| 307 | |
| 308 | int mtrr_set(int cpu_select, int reg, u64 base, u64 mask) |
| 309 | { |
| 310 | struct mtrr_oper oper; |
| 311 | |
| 312 | oper.opcode = MTRR_OP_SET; |
| 313 | oper.reg = reg; |
| 314 | oper.base = base; |
| 315 | oper.mask = mask; |
| 316 | |
| 317 | return mtrr_start_op(cpu_select, &oper); |
| 318 | } |