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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +09002/*
3 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
4 * Copyright (C) 2012 Renesas Solutions Corp.
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +09005 */
6
7#ifndef __KZM9G_H
8#define __KZM9G_H
9
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090010#define CONFIG_SH73A0
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090011#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
12
13#include <asm/arch/rmobile.h>
14
15#define CONFIG_ARCH_CPU_INIT
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090016
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090017#define CONFIG_CMDLINE_TAG
18#define CONFIG_SETUP_MEMORY_TAGS
19#define CONFIG_INITRD_TAG
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090020
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090021#undef CONFIG_SHOW_BOOT_PROGRESS
22
23/* MEMORY */
24#define KZM_SDRAM_BASE (0x40000000)
25#define PHYS_SDRAM KZM_SDRAM_BASE
26#define PHYS_SDRAM_SIZE (512 * 1024 * 1024)
27#define CONFIG_NR_DRAM_BANKS (1)
28
29/* NOR Flash */
30#define KZM_FLASH_BASE (0x00000000)
31#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE)
32#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
33#define CONFIG_SYS_MAX_FLASH_BANKS (1)
34#define CONFIG_SYS_MAX_FLASH_SECT (512)
35
36/* prompt */
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090037#define CONFIG_SYS_PBSIZE 256
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090038#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
39
40/* SCIF */
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090041#define CONFIG_CONS_SCIF4
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090042
43#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE)
44#define CONFIG_SYS_MEMTEST_END \
45 (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090046#undef CONFIG_SYS_MEMTEST_SCRATCH
47#undef CONFIG_SYS_LOADS_BAUD_CHANGE
48
49#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */
50#define CONFIG_SYS_INIT_RAM_SIZE (0x10000)
51#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4)
52#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
53 CONFIG_SYS_INIT_RAM_SIZE - \
54 GENERATED_GBL_DATA_SIZE)
Tetsuyuki Kobayashi6a8c5152012-07-05 01:43:44 +000055#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024)
56#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
57#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090058#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
59
60#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE)
61#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090062#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
63
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090064#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000
65
66/* FLASH */
67#define CONFIG_FLASH_CFI_DRIVER
68#define CONFIG_SYS_FLASH_CFI
69#undef CONFIG_SYS_FLASH_QUIET_TEST
70#define CONFIG_SYS_FLASH_EMPTY_INFO
71#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */
72#define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE
73#define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE
74#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
75
76/* Timeout for Flash erase operations (in ms) */
77#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
78/* Timeout for Flash write operations (in ms) */
79#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
80/* Timeout for Flash set sector lock bit operations (in ms) */
81#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
82/* Timeout for Flash clear lock bit operations (in ms) */
83#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
84
85#undef CONFIG_SYS_FLASH_PROTECTION
86#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090087
88/* GPIO / PFC */
89#define CONFIG_SH_GPIO_PFC
90
91/* Clock */
Nobuhiro Iwamatsu8c002362012-08-03 13:56:52 +090092#define CONFIG_GLOBAL_TIMER
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090093#define CONFIG_SYS_CLK_FREQ (48000000)
94#define CONFIG_SYS_CPU_CLK (1196000000)
Nobuhiro Iwamatsuadbaef52013-09-30 10:30:40 +090095#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090096#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090097
Tetsuyuki Kobayashi3d743272012-07-25 18:24:18 +000098#define CONFIG_NFS_TIMEOUT 10000UL
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +090099
100/* I2C */
Nobuhiro Iwamatsu12240102013-10-29 13:33:51 +0900101#define CONFIG_SYS_I2C
102#define CONFIG_SYS_I2C_SH
103#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
104#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000
105#define CONFIG_SYS_I2C_SH_SPEED0 100000
106#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000
107#define CONFIG_SYS_I2C_SH_SPEED1 100000
108#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000
109#define CONFIG_SYS_I2C_SH_SPEED2 100000
110#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000
111#define CONFIG_SYS_I2C_SH_SPEED3 100000
112#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000
113#define CONFIG_SYS_I2C_SH_SPEED4 100000
Tetsuyuki Kobayashicc4283c2012-09-13 19:07:56 +0000114#define CONFIG_SH_I2C_8BIT
Nobuhiro Iwamatsu12240102013-10-29 13:33:51 +0900115#define CONFIG_SH_I2C_DATA_HIGH 4
116#define CONFIG_SH_I2C_DATA_LOW 5
117#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */
Nobuhiro Iwamatsu06d4c6d2012-06-21 14:55:07 +0900118
119#endif /* __KZM9G_H */