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git01.mediatek.com / filogic / uboot / 49568feff1e123d4b24079b0b8e92704658912b6 / . / arch / powerpc / cpu / mpc86xx / release.S
blob: 72ad8834c979ece1729423b6a3d4277dab3f6ace [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Becky Bruced1cb6cb2008-11-03 15:44:01 -0600[diff] [blame]2/*
3 * Copyright 2004, 2007, 2008 Freescale Semiconductor.
4 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
Becky Bruced1cb6cb2008-11-03 15:44:01 -0600[diff] [blame]5 */
6#include <config.h>
7#include <mpc86xx.h>
Becky Bruced1cb6cb2008-11-03 15:44:01 -0600[diff] [blame]8
9#include <ppc_asm.tmpl>
10#include <ppc_defs.h>
11
12#include <asm/cache.h>
13#include <asm/mmu.h>
14
15/* If this is a multi-cpu system then we need to handle the
16 * 2nd cpu. The assumption is that the 2nd cpu is being
17 * held in boot holdoff mode until the 1st cpu unlocks it
18 * from Linux. We'll do some basic cpu init and then pass
19 * it to the Linux Reset Vector.
20 * Sri: Much of this initialization is not required. Linux
21 * rewrites the bats, and the sprs and also enables the L1 cache.
22 *
23 * Core 0 must copy this to a 1M aligned region and set BPTR
24 * to point to it.
25 */
Becky Bruced1cb6cb2008-11-03 15:44:01 -0600[diff] [blame]26 .align 12
27.globl __secondary_start_page
28__secondary_start_page:
29 .space 0x100 /* space over to reset vector loc */
30 mfspr r0, MSSCR0
31 andi. r0, r0, 0x0020
32 rlwinm r0,r0,27,31,31
33 mtspr PIR, r0
34
35 /* Invalidate BATs */
36 li r0, 0
37 mtspr IBAT0U, r0
38 mtspr IBAT1U, r0
39 mtspr IBAT2U, r0
40 mtspr IBAT3U, r0
41 mtspr IBAT4U, r0
42 mtspr IBAT5U, r0
43 mtspr IBAT6U, r0
44 mtspr IBAT7U, r0
45 isync
46 mtspr DBAT0U, r0
47 mtspr DBAT1U, r0
48 mtspr DBAT2U, r0
49 mtspr DBAT3U, r0
50 mtspr DBAT4U, r0
51 mtspr DBAT5U, r0
52 mtspr DBAT6U, r0
53 mtspr DBAT7U, r0
54 isync
55 sync
56
57 /* enable extended addressing */
58 mfspr r0, HID0
59 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
60 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
61 mtspr HID0, r0
62 sync
63 isync
64
65#ifdef CONFIG_SYS_L2
66 /* init the L2 cache */
67 addis r3, r0, L2_INIT@h
68 ori r3, r3, L2_INIT@l
69 sync
70 mtspr l2cr, r3
71#ifdef CONFIG_ALTIVEC
72 dssall
73#endif
74 /* invalidate the L2 cache */
75 mfspr r3, l2cr
76 rlwinm. r3, r3, 0, 0, 0
77 beq 1f
78
79 mfspr r3, l2cr
80 rlwinm r3, r3, 0, 1, 31
81
82#ifdef CONFIG_ALTIVEC
83 dssall
84#endif
85 sync
86 mtspr l2cr, r3
87 sync
881: mfspr r3, l2cr
89 oris r3, r3, L2CR_L2I@h
90 mtspr l2cr, r3
91
92invl2:
93 mfspr r3, l2cr
94 andis. r3, r3, L2CR_L2I@h
95 bne invl2
96 sync
97#endif
98
99 /* enable and invalidate the data cache */
100 mfspr r3, HID0
101 li r5, HID0_DCFI|HID0_DLOCK
102 andc r3, r3, r5
103 mtspr HID0, r3 /* no invalidate, unlock */
104 ori r3, r3, HID0_DCE
105 ori r5, r3, HID0_DCFI
106 mtspr HID0, r5 /* enable + invalidate */
107 mtspr HID0, r3 /* enable */
108 sync
Jean-Christophe PLAGNIOL-VILLARDf88438a2008-12-14 10:29:39 +0100[diff] [blame]109#ifdef CONFIG_SYS_L2
Becky Bruced1cb6cb2008-11-03 15:44:01 -0600[diff] [blame]110 sync
111 lis r3, L2_ENABLE@h
112 ori r3, r3, L2_ENABLE@l
113 mtspr l2cr, r3
114 isync
115 sync
116#endif
117
118 /* enable and invalidate the instruction cache*/
119 mfspr r3, HID0
120 li r5, HID0_ICFI|HID0_ILOCK
121 andc r3, r3, r5
122 ori r3, r3, HID0_ICE
123 ori r5, r3, HID0_ICFI
124 mtspr HID0, r5
125 mtspr HID0, r3
126 isync
127 sync
128
129 /* TBEN in HID0 */
130 mfspr r4, HID0
131 oris r4, r4, 0x0400
132 mtspr HID0, r4
133 sync
134 isync
135
136 /* MCP|SYNCBE|ABE in HID1 */
137 mfspr r4, HID1
138 oris r4, r4, 0x8000
139 ori r4, r4, 0x0C00
140 mtspr HID1, r4
141 sync
142 isync
143
144 lis r3, CONFIG_LINUX_RESET_VEC@h
145 ori r3, r3, CONFIG_LINUX_RESET_VEC@l
146 mtlr r3
147 blr
148
149 /* Never Returns, Running in Linux Now */