Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Kumar Gala | cdbe63d | 2010-07-08 05:24:44 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
Kumar Gala | cdbe63d | 2010-07-08 05:24:44 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <asm/fsl_serdes.h> |
| 8 | #include <asm/processor.h> |
| 9 | #include <asm/io.h> |
| 10 | #include "fsl_corenet_serdes.h" |
| 11 | |
| 12 | static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { |
| 13 | [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, |
| 14 | PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, |
| 15 | SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, |
| 16 | [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, |
| 17 | PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, |
| 18 | SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, }, |
| 19 | [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, |
| 20 | PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, |
| 21 | SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, |
| 22 | [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, |
| 23 | AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, |
| 24 | NONE, NONE, SATA1, SATA2, }, |
| 25 | [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, |
| 26 | AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
| 27 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, |
| 28 | [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, |
| 29 | AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
| 30 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, |
| 31 | XAUI_FM1, XAUI_FM1, }, |
| 32 | [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, |
| 33 | AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, |
| 34 | SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, |
| 35 | SGMII_FM1_DTSEC4, }, |
| 36 | [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, |
| 37 | AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, |
| 38 | NONE, NONE, SATA1, SATA2, }, |
| 39 | [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, |
| 40 | AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
| 41 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1, |
| 42 | SRIO1, }, |
| 43 | [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, |
| 44 | AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
| 45 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, |
| 46 | [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, |
| 47 | AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
| 48 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, |
| 49 | NONE, NONE, }, |
| 50 | [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, |
| 51 | AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, |
| 52 | NONE, NONE, SATA1, SATA2, }, |
| 53 | [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, |
| 54 | AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, |
| 55 | SATA1, SATA2, }, |
| 56 | [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, |
| 57 | AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
| 58 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, |
| 59 | XAUI_FM1, XAUI_FM1, }, |
| 60 | [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, |
| 61 | AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, |
| 62 | SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, |
| 63 | SGMII_FM1_DTSEC4, }, |
| 64 | [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, |
| 65 | AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, |
| 66 | NONE, NONE, SATA1, SATA2, }, |
| 67 | [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, |
| 68 | AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
| 69 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, |
| 70 | [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, |
| 71 | AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
| 72 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, |
| 73 | NONE, NONE, }, |
| 74 | [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, |
| 75 | AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
| 76 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, |
| 77 | [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, |
| 78 | AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
| 79 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, |
| 80 | NONE, NONE, }, |
| 81 | [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, |
| 82 | AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
| 83 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, |
| 84 | XAUI_FM1, XAUI_FM1, }, |
| 85 | [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, |
| 86 | AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, |
| 87 | NONE, NONE, SATA1, SATA2, }, |
| 88 | [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1, |
| 89 | AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, |
| 90 | NONE, NONE, SATA1, SATA2, }, |
| 91 | [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, |
| 92 | AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, |
| 93 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, |
| 94 | NONE, NONE, }, |
| 95 | [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, |
| 96 | AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, |
| 97 | NONE, NONE, SATA1, SATA2, }, |
| 98 | [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1, |
| 99 | SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, |
| 100 | AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, |
| 101 | NONE, SATA1, SATA2, }, |
| 102 | [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, |
| 103 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, |
| 104 | XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, |
| 105 | [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1, |
| 106 | SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, |
| 107 | AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, |
| 108 | NONE, SATA1, SATA2, }, |
| 109 | [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, |
| 110 | SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, |
| 111 | XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, |
| 112 | }; |
| 113 | |
| 114 | enum srds_prtcl serdes_get_prtcl(int cfg, int lane) |
| 115 | { |
| 116 | if (!serdes_lane_enabled(lane)) |
| 117 | return NONE; |
| 118 | |
| 119 | return serdes_cfg_tbl[cfg][lane]; |
| 120 | } |
| 121 | |
| 122 | int is_serdes_prtcl_valid(u32 prtcl) { |
| 123 | int i; |
| 124 | |
Axel Lin | ab95b09 | 2013-05-26 15:00:30 +0800 | [diff] [blame] | 125 | if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) |
Kumar Gala | cdbe63d | 2010-07-08 05:24:44 -0500 | [diff] [blame] | 126 | return 0; |
| 127 | |
| 128 | for (i = 0; i < SRDS_MAX_LANES; i++) { |
| 129 | if (serdes_cfg_tbl[prtcl][i] != NONE) |
| 130 | return 1; |
| 131 | } |
| 132 | |
| 133 | return 0; |
| 134 | } |