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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Bryan Wu97adb222014-06-24 11:45:29 +09002/*
Alexandre Courbot7f936d42015-07-09 16:33:00 +09003 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
Bryan Wu97adb222014-06-24 11:45:29 +09004 */
5
6/* Tegra vpr routines */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/tegra.h>
11#include <asm/arch/mc.h>
12
Alexandre Courbot7f936d42015-07-09 16:33:00 +090013#include <fdt_support.h>
14
15static bool _configured;
16
Alexandre Courbotf36729d2015-10-19 13:57:03 +090017void tegra_gpu_config(void)
Bryan Wu97adb222014-06-24 11:45:29 +090018{
19 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
20
21 /* Turn VPR off */
22 writel(0, &mc->mc_video_protect_size_mb);
23 writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
24 &mc->mc_video_protect_reg_ctrl);
25 /* read back to ensure the write went through */
26 readl(&mc->mc_video_protect_reg_ctrl);
Alexandre Courbot7f936d42015-07-09 16:33:00 +090027
28 debug("configured VPR\n");
29
30 _configured = true;
31}
32
Alexandre Courbot5e270dc2015-07-09 16:33:01 +090033#if defined(CONFIG_OF_LIBFDT)
34
Stephen Warrenf4949cd2016-04-12 11:17:39 -060035int tegra_gpu_enable_node(void *blob, const char *compat)
Alexandre Courbot5e270dc2015-07-09 16:33:01 +090036{
37 int offset;
38
Stephen Warrenf4949cd2016-04-12 11:17:39 -060039 if (!_configured)
40 return 0;
41
42 offset = fdt_node_offset_by_compatible(blob, -1, compat);
43 while (offset != -FDT_ERR_NOTFOUND) {
44 fdt_status_okay(blob, offset);
45 offset = fdt_node_offset_by_compatible(blob, offset, compat);
Alexandre Courbot5e270dc2015-07-09 16:33:01 +090046 }
47
48 return 0;
49}
50
51#endif