blob: 2aca24bbb0f8869c8a86cd00dcfbf033b025dcee [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Adrian Alonso2b3d9612015-09-02 13:54:19 -05002/*
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
Adrian Alonso2b3d9612015-09-02 13:54:19 -05004 */
5
6#include <common.h>
7#include <asm/io.h>
8#include <asm/arch/imx-regs.h>
9#include <asm/arch/clock.h>
10#include <asm/arch/sys_proto.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020011#include <asm/mach-imx/boot_mode.h>
12#include <asm/mach-imx/dma.h>
13#include <asm/mach-imx/hab.h>
14#include <asm/mach-imx/rdc-sema.h>
Peng Fan47842492016-01-28 16:55:09 +080015#include <asm/arch/imx-rdc.h>
Adrian Alonso2b3d9612015-09-02 13:54:19 -050016#include <asm/arch/crm_regs.h>
17#include <dm.h>
18#include <imx_thermal.h>
Bryan O'Donoghue1ec9d9d2018-01-26 16:27:58 +000019#include <fsl_sec.h>
Bryan O'Donoghue0cdded82018-03-26 15:27:32 +010020#include <asm/setup.h>
Adrian Alonso2b3d9612015-09-02 13:54:19 -050021
Adrian Alonso2b3d9612015-09-02 13:54:19 -050022#if defined(CONFIG_IMX_THERMAL)
23static const struct imx_thermal_plat imx7_thermal_plat = {
24 .regs = (void *)ANATOP_BASE_ADDR,
25 .fuse_bank = 3,
26 .fuse_word = 3,
27};
28
29U_BOOT_DEVICE(imx7_thermal) = {
30 .name = "imx_thermal",
31 .platdata = &imx7_thermal_plat,
32};
33#endif
34
Peng Fan77d3aeb2017-08-12 22:10:57 +080035#if CONFIG_IS_ENABLED(IMX_RDC)
Peng Fan47842492016-01-28 16:55:09 +080036/*
37 * In current design, if any peripheral was assigned to both A7 and M4,
38 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
39 * low power mode. So M4 sleep will cause some peripherals fail to work
40 * at A7 core side. At default, all resources are in domain 0 - 3.
41 *
42 * There are 26 peripherals impacted by this IC issue:
43 * SIM2(sim2/emvsim2)
44 * SIM1(sim1/emvsim1)
45 * UART1/UART2/UART3/UART4/UART5/UART6/UART7
46 * SAI1/SAI2/SAI3
47 * WDOG1/WDOG2/WDOG3/WDOG4
48 * GPT1/GPT2/GPT3/GPT4
49 * PWM1/PWM2/PWM3/PWM4
50 * ENET1/ENET2
51 * Software Workaround:
52 * Here we setup some resources to domain 0 where M4 codes will move
53 * the M4 out of this domain. Then M4 is not able to access them any longer.
54 * This is a workaround for ic issue. So the peripherals are not shared
55 * by them. This way requires the uboot implemented the RDC driver and
56 * set the 26 IPs above to domain 0 only. M4 code will assign resource
57 * to its own domain, if it want to use the resource.
58 */
59static rdc_peri_cfg_t const resources[] = {
60 (RDC_PER_SIM1 | RDC_DOMAIN(0)),
61 (RDC_PER_SIM2 | RDC_DOMAIN(0)),
62 (RDC_PER_UART1 | RDC_DOMAIN(0)),
63 (RDC_PER_UART2 | RDC_DOMAIN(0)),
64 (RDC_PER_UART3 | RDC_DOMAIN(0)),
65 (RDC_PER_UART4 | RDC_DOMAIN(0)),
66 (RDC_PER_UART5 | RDC_DOMAIN(0)),
67 (RDC_PER_UART6 | RDC_DOMAIN(0)),
68 (RDC_PER_UART7 | RDC_DOMAIN(0)),
69 (RDC_PER_SAI1 | RDC_DOMAIN(0)),
70 (RDC_PER_SAI2 | RDC_DOMAIN(0)),
71 (RDC_PER_SAI3 | RDC_DOMAIN(0)),
72 (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
73 (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
74 (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
75 (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
76 (RDC_PER_GPT1 | RDC_DOMAIN(0)),
77 (RDC_PER_GPT2 | RDC_DOMAIN(0)),
78 (RDC_PER_GPT3 | RDC_DOMAIN(0)),
79 (RDC_PER_GPT4 | RDC_DOMAIN(0)),
80 (RDC_PER_PWM1 | RDC_DOMAIN(0)),
81 (RDC_PER_PWM2 | RDC_DOMAIN(0)),
82 (RDC_PER_PWM3 | RDC_DOMAIN(0)),
83 (RDC_PER_PWM4 | RDC_DOMAIN(0)),
84 (RDC_PER_ENET1 | RDC_DOMAIN(0)),
85 (RDC_PER_ENET2 | RDC_DOMAIN(0)),
86};
87
88static void isolate_resource(void)
89{
90 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
91}
92#endif
93
Adrian Alonsofcc8cb32015-10-12 13:48:13 -050094#if defined(CONFIG_SECURE_BOOT)
95struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
96 .bank = 1,
97 .word = 3,
98};
99#endif
100
Fabio Estevamf6ced1b2016-02-28 12:33:17 -0300101static bool is_mx7d(void)
102{
103 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
104 struct fuse_bank *bank = &ocotp->bank[1];
105 struct fuse_bank1_regs *fuse =
106 (struct fuse_bank1_regs *)bank->fuse_regs;
107 int val;
108
109 val = readl(&fuse->tester4);
110 if (val & 1)
111 return false;
112 else
113 return true;
114}
115
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500116u32 get_cpu_rev(void)
117{
118 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
119 ANATOP_BASE_ADDR;
120 u32 reg = readl(&ccm_anatop->digprog);
121 u32 type = (reg >> 16) & 0xff;
122
Fabio Estevamf6ced1b2016-02-28 12:33:17 -0300123 if (!is_mx7d())
124 type = MXC_CPU_MX7S;
125
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500126 reg &= 0xff;
127 return (type << 12) | reg;
128}
129
130#ifdef CONFIG_REVISION_TAG
131u32 __weak get_board_rev(void)
132{
133 return get_cpu_rev();
134}
135#endif
136
Peng Fanfcd53ce2015-10-23 10:13:04 +0800137/* enable all periherial can be accessed in nosec mode */
138static void init_csu(void)
139{
140 int i = 0;
141 for (i = 0; i < CSU_NUM_REGS; i++)
142 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
143}
144
Peng Faneb518d52016-01-04 13:16:41 +0800145static void imx_enet_mdio_fixup(void)
146{
147 struct iomuxc_gpr_base_regs *gpr_regs =
148 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
149
150 /*
151 * The management data input/output (MDIO) requires open-drain,
152 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
153 * this feature. So to TO1.1, need to enable open drain by setting
154 * bits GPR0[8:7].
155 */
156
157 if (soc_rev() >= CHIP_REV_1_1) {
158 setbits_le32(&gpr_regs->gpr[0],
159 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
160 }
161}
162
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500163int arch_cpu_init(void)
164{
165 init_aips();
166
Peng Fanfcd53ce2015-10-23 10:13:04 +0800167 init_csu();
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500168 /* Disable PDE bit of WMCR register */
Fabio Estevam5f79d462017-11-23 10:55:33 -0200169 imx_wdog_disable_powerdown();
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500170
Peng Faneb518d52016-01-04 13:16:41 +0800171 imx_enet_mdio_fixup();
172
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500173#ifdef CONFIG_APBH_DMA
174 /* Start APBH DMA */
175 mxs_dma_init();
176#endif
177
Peng Fan77d3aeb2017-08-12 22:10:57 +0800178#if CONFIG_IS_ENABLED(IMX_RDC)
179 isolate_resource();
180#endif
Peng Fan47842492016-01-28 16:55:09 +0800181
Bryan O'Donoghue0290ea02018-04-05 19:46:06 +0100182 init_snvs();
183
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500184 return 0;
185}
186
Stefan Agner42dac202016-07-13 00:25:39 -0700187#ifdef CONFIG_ARCH_MISC_INIT
188int arch_misc_init(void)
189{
190#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
191 if (is_mx7d())
Simon Glass6a38e412017-08-03 12:22:09 -0600192 env_set("soc", "imx7d");
Stefan Agner42dac202016-07-13 00:25:39 -0700193 else
Simon Glass6a38e412017-08-03 12:22:09 -0600194 env_set("soc", "imx7s");
Stefan Agner42dac202016-07-13 00:25:39 -0700195#endif
196
Bryan O'Donoghue1ec9d9d2018-01-26 16:27:58 +0000197#ifdef CONFIG_FSL_CAAM
198 sec_init();
199#endif
200
Stefan Agner42dac202016-07-13 00:25:39 -0700201 return 0;
202}
203#endif
204
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500205#ifdef CONFIG_SERIAL_TAG
Bryan O'Donoghue3031d432018-03-26 15:27:33 +0100206/*
207 * OCOTP_TESTER
208 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
209 * OCOTP_TESTER describes a unique ID based on silicon wafer
210 * and die X/Y position
211 *
212 * OCOTOP_TESTER offset 0x410
213 * 31:0 fuse 0
214 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
215 *
216 * OCOTP_TESTER1 offset 0x420
217 * 31:24 fuse 1
218 * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
219 * 23:16 fuse 1
220 * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
221 * 15:11 fuse 1
222 * The wafer number of the wafer on which the device was fabricated/SJC
223 * CHALLENGE/ Unique ID
224 * 10:0 fuse 1
225 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
226 */
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500227void get_board_serial(struct tag_serialnr *serialnr)
228{
229 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
230 struct fuse_bank *bank = &ocotp->bank[0];
231 struct fuse_bank0_regs *fuse =
232 (struct fuse_bank0_regs *)bank->fuse_regs;
233
234 serialnr->low = fuse->tester0;
235 serialnr->high = fuse->tester1;
236}
237#endif
238
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500239void set_wdog_reset(struct wdog_regs *wdog)
240{
241 u32 reg = readw(&wdog->wcr);
242 /*
243 * Output WDOG_B signal to reset external pmic or POR_B decided by
244 * the board desgin. Without external reset, the peripherals/DDR/
245 * PMIC are not reset, that may cause system working abnormal.
246 */
247 reg = readw(&wdog->wcr);
248 reg |= 1 << 3;
249 /*
250 * WDZST bit is write-once only bit. Align this bit in kernel,
251 * otherwise kernel code will have no chance to set this bit.
252 */
253 reg |= 1 << 0;
254 writew(reg, &wdog->wcr);
255}
256
257/*
258 * cfg_val will be used for
259 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
260 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
261 * to SBMR1, which will determine the boot device.
262 */
263const struct boot_mode soc_boot_modes[] = {
264 {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
265 {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
266 {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
267 {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
268
269 {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
270 {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
271 /* 4 bit bus width */
272 {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
273 {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
274 {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
275 {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
276 {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
277 {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
278 {NULL, 0},
279};
280
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500281void s_init(void)
282{
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500283 /* clock configuration. */
284 clock_init();
285
286 return;
287}
Peng Fan99c874b2016-05-19 13:02:16 +0800288
289void reset_misc(void)
290{
291#ifdef CONFIG_VIDEO_MXS
292 lcdif_power_down();
293#endif
294}
295