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Lokesh Vutla5839b1c2019-06-13 10:29:53 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721E SoC Family
4 *
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/pinctrl/k3.h>
11#include <dt-bindings/soc/ti,sci_pm_domain.h>
12
13/ {
14 model = "Texas Instruments K3 J721E SoC";
15 compatible = "ti,j721e";
16 interrupt-parent = <&gic500>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 serial0 = &wkup_uart0;
22 serial1 = &mcu_uart0;
23 serial2 = &main_uart0;
24 serial3 = &main_uart1;
25 serial4 = &main_uart2;
26 serial5 = &main_uart3;
27 serial6 = &main_uart4;
28 serial7 = &main_uart5;
29 serial8 = &main_uart6;
30 serial9 = &main_uart7;
31 serial10 = &main_uart8;
32 serial11 = &main_uart9;
Vignesh Raghavendrae421d092020-01-27 23:22:13 +053033 i2c0 = &wkup_i2c0;
34 i2c1 = &mcu_i2c0;
35 i2c2 = &mcu_i2c1;
36 i2c3 = &main_i2c0;
37 i2c4 = &main_i2c1;
38 i2c5 = &main_i2c2;
39 i2c6 = &main_i2c3;
40 i2c7 = &main_i2c4;
41 i2c8 = &main_i2c5;
42 i2c9 = &main_i2c6;
Lokesh Vutla5839b1c2019-06-13 10:29:53 +053043 };
44
45 chosen { };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 cpu-map {
51 cluster0: cluster0 {
52 core0 {
53 cpu = <&cpu0>;
54 };
55
56 core1 {
57 cpu = <&cpu1>;
58 };
59 };
60
61 };
62
63 cpu0: cpu@0 {
64 compatible = "arm,cortex-a72";
65 reg = <0x000>;
66 device_type = "cpu";
67 enable-method = "psci";
68 i-cache-size = <0xC000>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <256>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&L2_0>;
75 };
76
77 cpu1: cpu@1 {
78 compatible = "arm,cortex-a72";
79 reg = <0x001>;
80 device_type = "cpu";
81 enable-method = "psci";
82 i-cache-size = <0xC000>;
83 i-cache-line-size = <64>;
84 i-cache-sets = <256>;
85 d-cache-size = <0x8000>;
86 d-cache-line-size = <64>;
87 d-cache-sets = <128>;
88 next-level-cache = <&L2_0>;
89 };
90 };
91
92 L2_0: l2-cache0 {
93 compatible = "cache";
94 cache-level = <2>;
95 cache-size = <0x100000>;
96 cache-line-size = <64>;
97 cache-sets = <2048>;
98 next-level-cache = <&msmc_l3>;
99 };
100
101 msmc_l3: l3-cache0 {
102 compatible = "cache";
103 cache-level = <3>;
104 };
105
106 firmware {
107 optee {
108 compatible = "linaro,optee-tz";
109 method = "smc";
110 };
111
112 psci: psci {
113 compatible = "arm,psci-1.0";
114 method = "smc";
115 };
116 };
117
118 a72_timer0: timer-cl0-cpu0 {
119 compatible = "arm,armv8-timer";
120 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
121 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
122 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
123 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
124 };
125
126 pmu: pmu {
127 compatible = "arm,armv8-pmuv3";
128 /* Recommendation from GIC500 TRM Table A.3 */
129 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
130 };
131
132 cbass_main: interconnect@100000 {
133 compatible = "simple-bus";
134 #address-cells = <2>;
135 #size-cells = <2>;
136 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
137 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
138 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
139 <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
140 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
141 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
142 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
143 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
144 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
145 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
146 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
147 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
148 /* MCUSS_WKUP Range */
149 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
150 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
151 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
152 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
153 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
154 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
155 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
156 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
157 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
158 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
159 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
160 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>,
161 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
162 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
163
164 cbass_mcu_wakeup: interconnect@28380000 {
165 compatible = "simple-bus";
166 #address-cells = <2>;
167 #size-cells = <2>;
168 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
169 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
170 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
171 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
172 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
173 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
174 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
175 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
176 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
177 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
178 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
179 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
180 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
181 };
182 };
183};
184
185/* Now include the peripherals for each bus segments */
186#include "k3-j721e-main.dtsi"
187#include "k3-j721e-mcu-wakeup.dtsi"