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git01.mediatek.com / filogic / uboot / 492b9e76b9c5fa29c3f410a8ed45d8a9f0c48f82 / . / cpu / mpc85xx / pci.c
blob: 60c1e611a7b1de338ae0740fd0496dbe68818739 [file] [log] [blame]
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]1/*
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]2 * Copyright 2004 Freescale Semiconductor.
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]3 * Copyright (C) 2003 Motorola Inc.
4 * Xianghua Xiao (x.xiao@motorola.com)
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * PCI Configuration space access support for MPC85xx PCI Bridge
27 */
28#include <common.h>
29#include <asm/cpm_85xx.h>
30#include <pci.h>
31
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]32
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]33#if defined(CONFIG_PCI)
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]34
wdenk492b9e72004-08-01 23:02:45 +0000[diff] [blame^]35void
36pci_mpc85xx_init(struct pci_controller *hose)
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]37{
wdenk492b9e72004-08-01 23:02:45 +0000[diff] [blame^]38 volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]39 volatile ccsr_pcix_t *pcix = &immap->im_pcix;
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]40
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]41 u16 reg16;
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]42
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]43 hose->first_busno = 0;
44 hose->last_busno = 0xff;
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]45
wdenk492b9e72004-08-01 23:02:45 +0000[diff] [blame^]46 pci_set_region(hose->regions + 0,
47 CFG_PCI1_MEM_BASE,
48 CFG_PCI1_MEM_PHYS,
49 CFG_PCI1_MEM_SIZE,
50 PCI_REGION_MEM);
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]51
wdenk492b9e72004-08-01 23:02:45 +0000[diff] [blame^]52 pci_set_region(hose->regions + 1,
53 CFG_PCI1_IO_BASE,
54 CFG_PCI1_IO_PHYS,
55 CFG_PCI1_IO_SIZE,
56 PCI_REGION_IO);
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]57
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]58 hose->region_count = 2;
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]59
wdenk492b9e72004-08-01 23:02:45 +0000[diff] [blame^]60 pci_setup_indirect(hose,
61 (CFG_IMMR+0x8000),
62 (CFG_IMMR+0x8004));
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]63
wdenk492b9e72004-08-01 23:02:45 +0000[diff] [blame^]64 pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]65 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
wdenk492b9e72004-08-01 23:02:45 +0000[diff] [blame^]66 pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]67
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]68 /*
69 * Clear non-reserved bits in status register.
70 */
wdenk492b9e72004-08-01 23:02:45 +0000[diff] [blame^]71 pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
72 pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]73
wdenk492b9e72004-08-01 23:02:45 +0000[diff] [blame^]74 pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
75 pcix->potear1 = 0x00000000;
76 pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]77 pcix->powbear1 = 0x00000000;
wdenk492b9e72004-08-01 23:02:45 +0000[diff] [blame^]78 pcix->powar1 = 0x8004401c; /* 512M MEM space */
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]79
wdenk492b9e72004-08-01 23:02:45 +0000[diff] [blame^]80 pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
81 pcix->potear2 = 0x00000000;
82 pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]83 pcix->powbear2 = 0x00000000;
wdenk492b9e72004-08-01 23:02:45 +0000[diff] [blame^]84 pcix->powar2 = 0x80088017; /* 16M IO space */
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]85
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]86 pcix->pitar1 = 0x00000000;
87 pcix->piwbar1 = 0x00000000;
88 pcix->piwar1 = 0xa0F5501f;
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]89
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]90 /*
91 * Hose scan.
92 */
wdenk492b9e72004-08-01 23:02:45 +0000[diff] [blame^]93 pci_register_hose(hose);
94 hose->last_busno = pci_hose_scan(hose);
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]95}
wdenk13eb2212004-07-09 23:27:13 +0000[diff] [blame]96
wdenk9c53f402003-10-15 23:53:47 +0000[diff] [blame]97#endif /* CONFIG_PCI */