Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 492b9e76b9c5fa29c3f410a8ed45d8a9f0c48f82 / . / board / zpc1900 / zpc1900.c
blob: 6d16a0d19286b665e227a7ed31762ebbfd9d033b [file] [log] [blame]
wdenk2f0812d2003-10-08 22:45:44 +0000[diff] [blame]1/*
2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2003 Arabella Software Ltd.
6 * Yuli Barcohen <yuli@arabellasw.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <ioports.h>
29#include <mpc8260.h>
30#include <asm/m8260_pci.h>
31#include <i2c.h>
32#include <spd.h>
33#include <miiphy.h>
34
35/*
36 * I/O Port configuration table
37 *
38 * if conf is 1, then that port pin will be configured at boot time
39 * according to the five values podr/pdir/ppar/psor/pdat for that entry
40 */
41
42const iop_conf_t iop_conf_tab[4][32] = {
43
44 /* Port A */
45 { /* conf ppar psor pdir podr pdat */
46 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
47 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
48 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
49 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
50 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
51 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
52 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
53 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
54 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
55 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
56 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
57 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
58 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
59 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
60 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
61 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
62 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
63 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
64 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
65 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
66 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
67 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
68 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* SMC2 TXD */
69 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
70 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
71 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
72 /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
73 /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
74 /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
75 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
76 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
77 /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
78 },
79
80 /* Port B */
81 { /* conf ppar psor pdir podr pdat */
82 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
83 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
84 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
85 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
86 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
87 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
88 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
89 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
90 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
91 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
92 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
93 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
94 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
95 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
96 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
97 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
98 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
99 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
100 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
101 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
102 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
103 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
104 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
105 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
106 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
107 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
108 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
109 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
110 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
111 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
112 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
113 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
114 },
115
116 /* Port C */
117 { /* conf ppar psor pdir podr pdat */
118 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
119 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
120 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN CLSN */
121 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
122 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
123 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
124 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
125 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
126 /* PC23 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
127 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
128 /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
129 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
130 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
131 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
132 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
133 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
134 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
135 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RENA */
136 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
137 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
138 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
139 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT972 MDC */
140 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT972 MDIO */
141 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
142 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
143 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
144 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
145 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
146 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
147 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
148 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
149 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
150 },
151
152 /* Port D */
153 { /* conf ppar psor pdir podr pdat */
154 /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
155 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
156 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
157 /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
158 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
159 /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
160 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
161 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
162 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
163 /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
164 /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
165 /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
166 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
167 /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
168 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
169 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
170 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
171 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
172 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
173 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
174 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
175 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
176 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
177 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
178 /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
179 /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
180 /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
181 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
182 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
183 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
184 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
185 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
186 }
187};
188
189#ifdef CFG_NVRAM_ACCESS_ROUTINE
190void *nvram_read(void *dest, long src, size_t count)
191{
192 return memcpy(dest, (const void *)src, count);
193}
194
195void nvram_write(long dest, const void *src, size_t count)
196{
197 vu_char *p1 = (vu_char *)(CFG_EEPROM + 0x1555);
198 vu_char *p2 = (vu_char *)(CFG_EEPROM + 0x0AAA);
199 vu_char *d = (vu_char *)dest;
200 const uchar *s = (const uchar *)src;
201
202 /* Unprotect the EEPROM */
203 *p1 = 0xAA;
204 *p2 = 0x55;
205 *p1 = 0x80;
206 *p1 = 0xAA;
207 *p2 = 0x55;
208 *p1 = 0x20;
209 udelay(10000);
210
211 /* Write the data to the EEPROM */
212 while (count--) {
213 *d++ = *s++;
214 while (*(d - 1) != *(s - 1))
215 /* wait */;
216 }
217
218 /* Protect the EEPROM */
219 *p1 = 0xAA;
220 *p2 = 0x55;
221 *p1 = 0xA0;
222 udelay(10000);
223}
224#endif /* CFG_NVRAM_ACCESS_ROUTINE */
225
226long int initdram(int board_type)
227{
228 vu_char *bcsr = (vu_char *)CFG_BCSR;
229 volatile immap_t *immap = (immap_t *)CFG_IMMR;
230 volatile memctl8260_t *memctl = &immap->im_memctl;
231 vu_char *ramaddr;
232 uchar c = 0xFF;
233 long int msize = CFG_SDRAM_SIZE;
234 uint psdmr = CFG_PSDMR;
235 int i;
236
237 if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
238 immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
239 immap->im_siu_conf.sc_siumcr =
240 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
241 | SIUMCR_LBPC01;
242 }
243
244#ifndef CFG_RAMBOOT
245 immap->im_siu_conf.sc_ppc_acr = 0x03;
246 immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
247 immap->im_siu_conf.sc_tescr1 = 0x00004000;
248
249 memctl->memc_mptpr = CFG_MPTPR;
250
251#ifdef CFG_LSDRAM_BASE
252 /*
253 Initialise local bus SDRAM only if the pins
254 are configured as local bus pins and not as PCI.
255 */
256 if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
257 memctl->memc_lsrt = CFG_LSRT;
258 memctl->memc_or4 = 0xFFC01480;
259 memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
260 memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
261 ramaddr = (vu_char *)CFG_LSDRAM_BASE;
262 *ramaddr = c;
263 memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR;
264 for (i = 0; i < 8; i++)
265 *ramaddr = c;
266 memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_MRW;
267 *ramaddr = c;
268 memctl->memc_lsdmr = CFG_LSDMR | PSDMR_RFEN;
269 }
270#endif /* CFG_LSDRAM_BASE */
271
272 /* Initialise 60x bus SDRAM */
273 memctl->memc_psrt = CFG_PSRT;
274 memctl->memc_or2 = 0xFC0028C0;
275 memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
276 /*
277 * The mode data for Mode Register Write command must appear on
278 * the address lines during a mode-set cycle. It is driven by
279 * the memory controller, in single PowerQUICC II mode,
280 * according to PSDMR[CL] and PSDMR[BL] fields. In
281 * 60x-compatible mode, software must drive the correct value on
282 * the address lines. BL=0 because for 64-bit port size burst
283 * length must be 4.
284 */
285 ramaddr = (vu_char *)(CFG_SDRAM_BASE |
286 ((psdmr & PSDMR_CL_MSK) << 7) | 0x10);
287 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
288 *ramaddr = c;
289 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
290 for (i = 0; i < 8; i++)
291 *ramaddr = c;
292 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
293 *ramaddr = c;
294 memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
295 *ramaddr = c;
296#endif /* CFG_RAMBOOT */
297
298 /* Return total 60x bus SDRAM size */
299 return msize * 1024 * 1024;
300}
301
302int checkboard(void)
303{
304 vu_char *bcsr = (vu_char *)CFG_BCSR;
305
306 printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40);
307 return 0;
308}