| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | * Atmel SDHCI controller |
| 2 | |
| 3 | This file documents the differences between the core properties in |
| 4 | Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the |
| 5 | sdhci-of-at91 driver. |
| 6 | |
| 7 | Required properties: |
| 8 | - compatible: Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci" |
| 9 | or "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci". |
| 10 | - clocks: Phandlers to the clocks. |
| 11 | - clock-names: Must be "hclock", "multclk", "baseclk" for |
| 12 | "atmel,sama5d2-sdhci". |
| 13 | Must be "hclock", "multclk" for "microchip,sam9x60-sdhci". |
| 14 | Must be "hclock", "multclk" for "microchip,sam9x7-sdhci". |
| 15 | |
| 16 | Optional properties: |
| 17 | - assigned-clocks: The same with "multclk". |
| 18 | - assigned-clock-rates The rate of "multclk" in order to not rely on the |
| 19 | gck configuration set by previous components. |
| 20 | - microchip,sdcal-inverted: when present, polarity on the SDCAL SoC pin is |
| 21 | inverted. The default polarity for this signal is described in the datasheet. |
| 22 | For instance on SAMA5D2, the pin is usually tied to the GND with a resistor |
| 23 | and a capacitor (see "SDMMC I/O Calibration" chapter). |
| 24 | |
| 25 | Example: |
| 26 | |
| 27 | mmc0: sdio-host@a0000000 { |
| 28 | compatible = "atmel,sama5d2-sdhci"; |
| 29 | reg = <0xa0000000 0x300>; |
| 30 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; |
| 31 | clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>; |
| 32 | clock-names = "hclock", "multclk", "baseclk"; |
| 33 | assigned-clocks = <&sdmmc0_gclk>; |
| 34 | assigned-clock-rates = <480000000>; |
| 35 | }; |