Blame - dts/upstream/include/dt-bindings/reset/mt8195-resets.h - filogic/uboot

Tom Rini

53633a8

2024-02-29 12:33:36 -0500

[diff] [blame]

1

/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/

2

/*

3

4

* Author: Christine Zhu <christine.zhu@mediatek.com>

5

*/

6

7

#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195

8

#define _DT_BINDINGS_RESET_CONTROLLER_MT8195

9

10

/* TOPRGU resets */

11

#define MT8195_TOPRGU_CONN_MCU_SW_RST 0

12

#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1

13

#define MT8195_TOPRGU_APU_SW_RST 2

14

#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6

15

#define MT8195_TOPRGU_MMSYS_SW_RST 7

16

#define MT8195_TOPRGU_MFG_SW_RST 8

17

#define MT8195_TOPRGU_VENC_SW_RST 9

18

#define MT8195_TOPRGU_VDEC_SW_RST 10

19

#define MT8195_TOPRGU_IMG_SW_RST 11

20

#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13

21

#define MT8195_TOPRGU_AUDIO_SW_RST 14

22

#define MT8195_TOPRGU_CAMSYS_SW_RST 15

23

#define MT8195_TOPRGU_EDPTX_SW_RST 16

24

#define MT8195_TOPRGU_ADSPSYS_SW_RST 21

25

#define MT8195_TOPRGU_DPTX_SW_RST 22

26

#define MT8195_TOPRGU_SPMI_MST_SW_RST 23

27

28

#define MT8195_TOPRGU_SW_RST_NUM 16

29

30

/* INFRA resets */

31

#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0

32

#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1

33

#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2

34

#define MT8195_INFRA_RST2_PCIE_P0_SWRST 3

35

#define MT8195_INFRA_RST2_PCIE_P1_SWRST 4

36

#define MT8195_INFRA_RST2_USBSIF_P1_SWRST 5

37

38

/* VDOSYS1 */

39

#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2 0

40

#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB3 1

41

#define MT8195_VDOSYS1_SW0_RST_B_GALS 2

42

#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG0 3

43

#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG1 4

44

#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA0 5

45

#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA1 6

46

#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA2 7

47

#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA3 8

48

#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE0 9

49

#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE1 10

50

#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE2 11

51

#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE3 12

52

#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE4 13

53

#define MT8195_VDOSYS1_SW0_RST_B_VPP2_TO_VDO1_DL_ASYNC 14

54

#define MT8195_VDOSYS1_SW0_RST_B_VPP3_TO_VDO1_DL_ASYNC 15

55

#define MT8195_VDOSYS1_SW0_RST_B_DISP_MUTEX 16

56

#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA4 17

57

#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA5 18

58

#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA6 19

59

#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA7 20

60

#define MT8195_VDOSYS1_SW0_RST_B_DP_INTF0 21

61

#define MT8195_VDOSYS1_SW0_RST_B_DPI0 22

62

#define MT8195_VDOSYS1_SW0_RST_B_DPI1 23

63

#define MT8195_VDOSYS1_SW0_RST_B_DISP_MONITOR 24

64

#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25

65

#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26

66

#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27

67

#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28

68

#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29

69

#define MT8195_VDOSYS1_SW0_RST_B_VDO0_DSC_TO_VDO1_DL_ASYNC 30

70

#define MT8195_VDOSYS1_SW0_RST_B_VDO0_MERGE_TO_VDO1_DL_ASYNC 31

71

#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0 32

72

#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0 33

73

#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE 34

74

#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1 48

75

#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1 49

76

#define MT8195_VDOSYS1_SW1_RST_B_DISP_MIXER 50

77

#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51

78

#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52

79

#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53

80

#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54

81

#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55

82

83

#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */