| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * Copyright Intel Corporation (C) 2017. All Rights Reserved |
| 4 | * |
| 5 | * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip |
| 6 | * |
| 7 | * Adapted from altr,rst-mgr-a10.h |
| 8 | */ |
| 9 | |
| 10 | #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H |
| 11 | #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H |
| 12 | |
| 13 | /* Peripheral PHY resets */ |
| 14 | #define A10SR_RESET_ENET_HPS 0 |
| 15 | #define A10SR_RESET_PCIE 1 |
| 16 | #define A10SR_RESET_FILE 2 |
| 17 | #define A10SR_RESET_BQSPI 3 |
| 18 | #define A10SR_RESET_USB 4 |
| 19 | |
| 20 | #define A10SR_RESET_NUM 5 |
| 21 | |
| 22 | #endif |