Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
Yangbo Lu | bb32e68 | 2021-06-03 10:51:19 +0800 | [diff] [blame] | 3 | * Copyright 2018-2021 NXP |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __LX2_COMMON_H |
| 7 | #define __LX2_COMMON_H |
| 8 | |
| 9 | #include <asm/arch/stream_id_lsch3.h> |
| 10 | #include <asm/arch/config.h> |
| 11 | #include <asm/arch/soc.h> |
| 12 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 13 | #define CFG_SYS_FLASH_BASE 0x20000000 |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 14 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 15 | /* DDR */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 16 | #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 17 | #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 18 | #define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 19 | #define CFG_SYS_SDRAM_SIZE 0x200000000UL |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 20 | #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 21 | #define SPD_EEPROM_ADDRESS1 0x51 |
| 22 | #define SPD_EEPROM_ADDRESS2 0x52 |
| 23 | #define SPD_EEPROM_ADDRESS3 0x53 |
| 24 | #define SPD_EEPROM_ADDRESS4 0x54 |
| 25 | #define SPD_EEPROM_ADDRESS5 0x55 |
| 26 | #define SPD_EEPROM_ADDRESS6 0x56 |
| 27 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 28 | |
| 29 | /* Miscellaneous configurable options */ |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 30 | |
| 31 | /* SMP Definitinos */ |
Michael Walle | f056e0f | 2020-06-01 21:53:26 +0200 | [diff] [blame] | 32 | #define CPU_RELEASE_ADDR secondary_boot_addr |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 33 | |
| 34 | /* Generic Timer Definitions */ |
| 35 | /* |
| 36 | * This is not an accurate number. It is used in start.S. The frequency |
| 37 | * will be udpated later when get_bus_freq(0) is available. |
| 38 | */ |
| 39 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 40 | /* Serial Port */ |
Tom Rini | 5c896ae | 2022-12-04 10:13:30 -0500 | [diff] [blame] | 41 | #define CFG_PL011_CLOCK (get_bus_freq(0) / 4) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 42 | #define CFG_SYS_SERIAL0 0x21c0000 |
| 43 | #define CFG_SYS_SERIAL1 0x21d0000 |
| 44 | #define CFG_SYS_SERIAL2 0x21e0000 |
| 45 | #define CFG_SYS_SERIAL3 0x21f0000 |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 46 | /*below might needs to be removed*/ |
Tom Rini | 9fe2b31 | 2022-12-04 10:13:31 -0500 | [diff] [blame] | 47 | #define CFG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 48 | (void *)CFG_SYS_SERIAL1, \ |
| 49 | (void *)CFG_SYS_SERIAL2, \ |
| 50 | (void *)CFG_SYS_SERIAL3 } |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 51 | |
| 52 | /* MC firmware */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 53 | #define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 |
| 54 | #define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 |
| 55 | #define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 |
| 56 | #define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 |
| 57 | #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 58 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 59 | /* |
| 60 | * Carve out a DDR region which will not be used by u-boot/Linux |
| 61 | * |
| 62 | * It will be used by MC and Debug Server. The MC region must be |
| 63 | * 512MB aligned, so the min size to hide is 512MB. |
| 64 | */ |
| 65 | #ifdef CONFIG_FSL_MC_ENET |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 66 | #define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 67 | #endif |
| 68 | |
| 69 | /* I2C bus multiplexer */ |
| 70 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ |
| 71 | #define I2C_MUX_CH_DEFAULT 0x8 |
| 72 | |
| 73 | /* RTC */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 74 | #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 75 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 76 | /* Qixis */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 77 | #define CFG_SYS_I2C_FPGA_ADDR 0x66 |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 78 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 79 | /* USB */ |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 80 | |
Tom Rini | 8c70baa | 2021-12-14 13:36:40 -0500 | [diff] [blame] | 81 | #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 82 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 83 | #define HWCONFIG_BUFFER_SIZE 128 |
| 84 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 85 | /* Initial environment variables */ |
Kuldeep Singh | 3e78c33 | 2020-03-12 15:13:00 +0530 | [diff] [blame] | 86 | #define XSPI_MC_INIT_CMD \ |
| 87 | "sf probe 0:0 && " \ |
| 88 | "sf read 0x80640000 0x640000 0x80000 && " \ |
Priyanka Jain | 5fde164 | 2021-08-18 12:37:03 +0530 | [diff] [blame] | 89 | "sf read $fdt_addr_r 0xf00000 0x100000 && " \ |
Kuldeep Singh | 3e78c33 | 2020-03-12 15:13:00 +0530 | [diff] [blame] | 90 | "env exists secureboot && " \ |
| 91 | "esbc_validate 0x80640000 && " \ |
| 92 | "esbc_validate 0x80680000; " \ |
| 93 | "sf read 0x80a00000 0xa00000 0x300000 && " \ |
| 94 | "sf read 0x80e00000 0xe00000 0x100000; " \ |
| 95 | "fsl_mc start mc 0x80a00000 0x80e00000\0" |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 96 | |
| 97 | #define SD_MC_INIT_CMD \ |
Pankaj Bansal | 1972a53 | 2019-07-17 10:33:54 +0000 | [diff] [blame] | 98 | "mmc read 0x80a00000 0x5000 0x1200;" \ |
| 99 | "mmc read 0x80e00000 0x7000 0x800;" \ |
Priyanka Jain | 5fde164 | 2021-08-18 12:37:03 +0530 | [diff] [blame] | 100 | "mmc read $fdt_addr_r 0x7800 0x800;" \ |
Udit Agarwal | f34581e | 2018-12-14 04:43:32 +0000 | [diff] [blame] | 101 | "env exists secureboot && " \ |
Priyanka Singh | e29ef97 | 2020-01-22 10:31:22 +0000 | [diff] [blame] | 102 | "mmc read 0x80640000 0x3200 0x20 && " \ |
| 103 | "mmc read 0x80680000 0x3400 0x20 && " \ |
| 104 | "esbc_validate 0x80640000 && " \ |
| 105 | "esbc_validate 0x80680000 ;" \ |
Pankaj Bansal | 1972a53 | 2019-07-17 10:33:54 +0000 | [diff] [blame] | 106 | "fsl_mc start mc 0x80a00000 0x80e00000\0" |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 107 | |
Meenakshi Aggarwal | e181a3d | 2020-04-27 19:56:40 +0530 | [diff] [blame] | 108 | #define SD2_MC_INIT_CMD \ |
| 109 | "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \ |
| 110 | "mmc read 0x80e00000 0x7000 0x800;" \ |
Priyanka Jain | 5fde164 | 2021-08-18 12:37:03 +0530 | [diff] [blame] | 111 | "mmc read $fdt_addr_r 0x7800 0x800;" \ |
Meenakshi Aggarwal | e181a3d | 2020-04-27 19:56:40 +0530 | [diff] [blame] | 112 | "env exists secureboot && " \ |
| 113 | "mmc read 0x80640000 0x3200 0x20 && " \ |
| 114 | "mmc read 0x80680000 0x3400 0x20 && " \ |
| 115 | "esbc_validate 0x80640000 && " \ |
| 116 | "esbc_validate 0x80680000 ;" \ |
| 117 | "fsl_mc start mc 0x80a00000 0x80e00000\0" |
| 118 | |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 119 | #define EXTRA_ENV_SETTINGS \ |
| 120 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
| 121 | "ramdisk_addr=0x800000\0" \ |
| 122 | "ramdisk_size=0x2000000\0" \ |
| 123 | "fdt_high=0xa0000000\0" \ |
| 124 | "initrd_high=0xffffffffffffffff\0" \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 125 | "kernel_start=0x1000000\0" \ |
Priyanka Singh | e29ef97 | 2020-01-22 10:31:22 +0000 | [diff] [blame] | 126 | "kernelheader_start=0x600000\0" \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 127 | "scriptaddr=0x80000000\0" \ |
| 128 | "scripthdraddr=0x80080000\0" \ |
| 129 | "fdtheader_addr_r=0x80100000\0" \ |
| 130 | "kernelheader_addr_r=0x80200000\0" \ |
| 131 | "kernel_addr_r=0x81000000\0" \ |
| 132 | "kernelheader_size=0x40000\0" \ |
| 133 | "fdt_addr_r=0x90000000\0" \ |
| 134 | "load_addr=0xa0000000\0" \ |
| 135 | "kernel_size=0x2800000\0" \ |
| 136 | "kernel_addr_sd=0x8000\0" \ |
Priyanka Singh | e29ef97 | 2020-01-22 10:31:22 +0000 | [diff] [blame] | 137 | "kernelhdr_addr_sd=0x3000\0" \ |
Manish Tomar | ebef67f | 2020-11-05 14:08:56 +0530 | [diff] [blame] | 138 | "kernel_size_sd=0x14000\0" \ |
Udit Agarwal | 11e1a57 | 2019-11-20 08:49:06 +0000 | [diff] [blame] | 139 | "kernelhdr_size_sd=0x20\0" \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 140 | "console=ttyAMA0,38400n8\0" \ |
| 141 | BOOTENV \ |
| 142 | "mcmemsize=0x70000000\0" \ |
| 143 | XSPI_MC_INIT_CMD \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 144 | "scan_dev_for_boot_part=" \ |
| 145 | "part list ${devtype} ${devnum} devplist; " \ |
| 146 | "env exists devplist || setenv devplist 1; " \ |
| 147 | "for distro_bootpart in ${devplist}; do " \ |
| 148 | "if fstype ${devtype} " \ |
| 149 | "${devnum}:${distro_bootpart} " \ |
| 150 | "bootfstype; then " \ |
| 151 | "run scan_dev_for_boot; " \ |
| 152 | "fi; " \ |
| 153 | "done\0" \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 154 | "boot_a_script=" \ |
| 155 | "load ${devtype} ${devnum}:${distro_bootpart} " \ |
| 156 | "${scriptaddr} ${prefix}${script}; " \ |
| 157 | "env exists secureboot && load ${devtype} " \ |
| 158 | "${devnum}:${distro_bootpart} " \ |
| 159 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ |
| 160 | "&& esbc_validate ${scripthdraddr};" \ |
| 161 | "source ${scriptaddr}\0" |
| 162 | |
| 163 | #define XSPI_NOR_BOOTCOMMAND \ |
Kuldeep Singh | 3e78c33 | 2020-03-12 15:13:00 +0530 | [diff] [blame] | 164 | "sf probe 0:0; " \ |
| 165 | "sf read 0x806c0000 0x6c0000 0x40000; " \ |
| 166 | "env exists mcinitcmd && env exists secureboot" \ |
| 167 | " && esbc_validate 0x806c0000; " \ |
| 168 | "sf read 0x80d00000 0xd00000 0x100000; " \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 169 | "env exists mcinitcmd && " \ |
Kuldeep Singh | 3e78c33 | 2020-03-12 15:13:00 +0530 | [diff] [blame] | 170 | "fsl_mc lazyapply dpl 0x80d00000; " \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 171 | "run distro_bootcmd;run xspi_bootcmd; " \ |
| 172 | "env exists secureboot && esbc_halt;" |
| 173 | |
| 174 | #define SD_BOOTCOMMAND \ |
| 175 | "env exists mcinitcmd && mmcinfo; " \ |
Pankaj Bansal | 1972a53 | 2019-07-17 10:33:54 +0000 | [diff] [blame] | 176 | "mmc read 0x80d00000 0x6800 0x800; " \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 177 | "env exists mcinitcmd && env exists secureboot " \ |
Priyanka Singh | e29ef97 | 2020-01-22 10:31:22 +0000 | [diff] [blame] | 178 | " && mmc read 0x806C0000 0x3600 0x20 " \ |
| 179 | "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ |
Pankaj Bansal | 1972a53 | 2019-07-17 10:33:54 +0000 | [diff] [blame] | 180 | "&& fsl_mc lazyapply dpl 0x80d00000;" \ |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 181 | "run distro_bootcmd;run sd_bootcmd;" \ |
| 182 | "env exists secureboot && esbc_halt;" |
| 183 | |
Meenakshi Aggarwal | bebebab | 2020-02-19 23:30:45 +0530 | [diff] [blame] | 184 | #define SD2_BOOTCOMMAND \ |
Meenakshi Aggarwal | e181a3d | 2020-04-27 19:56:40 +0530 | [diff] [blame] | 185 | "mmc dev 1; env exists mcinitcmd && mmcinfo; " \ |
Meenakshi Aggarwal | bebebab | 2020-02-19 23:30:45 +0530 | [diff] [blame] | 186 | "mmc read 0x80d00000 0x6800 0x800; " \ |
| 187 | "env exists mcinitcmd && env exists secureboot " \ |
Meenakshi Aggarwal | e181a3d | 2020-04-27 19:56:40 +0530 | [diff] [blame] | 188 | " && mmc read 0x806C0000 0x3600 0x20 " \ |
| 189 | "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ |
Meenakshi Aggarwal | bebebab | 2020-02-19 23:30:45 +0530 | [diff] [blame] | 190 | "&& fsl_mc lazyapply dpl 0x80d00000;" \ |
| 191 | "run distro_bootcmd;run sd2_bootcmd;" \ |
| 192 | "env exists secureboot && esbc_halt;" |
| 193 | |
Daniel Klauer | d7daa55 | 2022-02-09 15:53:41 +0100 | [diff] [blame] | 194 | #ifdef CONFIG_CMD_USB |
| 195 | #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) |
| 196 | #else |
| 197 | #define BOOT_TARGET_DEVICES_USB(func) |
| 198 | #endif |
| 199 | |
| 200 | #ifdef CONFIG_MMC |
| 201 | #define BOOT_TARGET_DEVICES_MMC(func, instance) func(MMC, mmc, instance) |
| 202 | #else |
| 203 | #define BOOT_TARGET_DEVICES_MMC(func) |
| 204 | #endif |
| 205 | |
| 206 | #ifdef CONFIG_SCSI |
| 207 | #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) |
| 208 | #else |
| 209 | #define BOOT_TARGET_DEVICES_SCSI(func) |
| 210 | #endif |
| 211 | |
| 212 | #ifdef CONFIG_CMD_DHCP |
| 213 | #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) |
| 214 | #else |
| 215 | #define BOOT_TARGET_DEVICES_DHCP(func) |
| 216 | #endif |
| 217 | |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 218 | #define BOOT_TARGET_DEVICES(func) \ |
Daniel Klauer | d7daa55 | 2022-02-09 15:53:41 +0100 | [diff] [blame] | 219 | BOOT_TARGET_DEVICES_USB(func) \ |
| 220 | BOOT_TARGET_DEVICES_MMC(func, 0) \ |
| 221 | BOOT_TARGET_DEVICES_MMC(func, 1) \ |
| 222 | BOOT_TARGET_DEVICES_SCSI(func) \ |
| 223 | BOOT_TARGET_DEVICES_DHCP(func) |
Priyanka Jain | 1674406 | 2019-01-24 05:22:18 +0000 | [diff] [blame] | 224 | #include <config_distro_bootcmd.h> |
| 225 | |
Priyanka Jain | fd45ca0 | 2018-11-28 13:04:27 +0000 | [diff] [blame] | 226 | #endif /* __LX2_COMMON_H */ |