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git01.mediatek.com / filogic / uboot / 48cd90054377de0e788bfda1b33c12fee1a209b1 / . / drivers / pinctrl / rockchip / pinctrl_rv1108.c
blob: cda94f49575911b3ea22d4400c2c194d905f163a [file] [log] [blame]
Andy Yan96c3da92017-06-01 18:00:10 +0800[diff] [blame]1/*
2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3 * Author: Andy Yan <andy.yan@rock-chips.com>
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#include <common.h>
7#include <dm.h>
8#include <errno.h>
9#include <syscon.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/grf_rv1108.h>
13#include <asm/arch/hardware.h>
14#include <asm/arch/periph.h>
15#include <dm/pinctrl.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19struct rv1108_pinctrl_priv {
20 struct rv1108_grf *grf;
21};
22
23static void pinctrl_rv1108_uart_config(struct rv1108_grf *grf, int uart_id)
24{
25 switch (uart_id) {
26 case PERIPH_ID_UART0:
27 rk_clrsetreg(&grf->gpio3a_iomux,
28 GPIO3A6_MASK | GPIO3A5_MASK,
29 GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT |
30 GPIO3A5_UART1_SIN << GPIO3A5_SHIFT);
31 break;
32 case PERIPH_ID_UART1:
33 rk_clrsetreg(&grf->gpio1d_iomux,
34 GPIO1D3_MASK | GPIO1D2_MASK | GPIO1D1_MASK |
35 GPIO1D0_MASK,
36 GPIO1D3_UART0_SOUT << GPIO1D3_SHIFT |
37 GPIO1D2_UART0_SIN << GPIO1D2_SHIFT |
38 GPIO1D1_UART0_RTSN << GPIO1D1_SHIFT |
39 GPIO1D0_UART0_CTSN << GPIO1D0_SHIFT);
40 break;
41 case PERIPH_ID_UART2:
42 rk_clrsetreg(&grf->gpio2d_iomux,
43 GPIO2D2_MASK | GPIO2D1_MASK,
44 GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
45 GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
46 break;
47 }
48}
49
50static void pinctrl_rv1108_gmac_config(struct rv1108_grf *grf, int func)
51{
52 rk_clrsetreg(&grf->gpio1b_iomux,
53 GPIO1B7_MASK | GPIO1B6_MASK | GPIO1B5_MASK |
54 GPIO1B4_MASK | GPIO1B3_MASK | GPIO1B2_MASK,
55 GPIO1B7_GMAC_RXDV << GPIO1B7_SHIFT |
56 GPIO1B6_GMAC_RXD1 << GPIO1B6_SHIFT |
57 GPIO1B5_GMAC_RXD0 << GPIO1B5_SHIFT |
58 GPIO1B4_GMAC_TXEN << GPIO1B4_SHIFT |
59 GPIO1B3_GMAC_TXD1 << GPIO1B3_SHIFT |
60 GPIO1B2_GMAC_TXD0 << GPIO1B2_SHIFT);
61 rk_clrsetreg(&grf->gpio1c_iomux,
62 GPIO1C5_MASK | GPIO1C4_MASK |
63 GPIO1C3_MASK | GPIO1C2_MASK,
64 GPIO1C5_GMAC_CLK << GPIO1C5_SHIFT |
65 GPIO1C4_GMAC_MDC << GPIO1C4_SHIFT |
66 GPIO1C3_GMAC_MDIO << GPIO1C3_SHIFT |
67 GPIO1C2_GMAC_RXER << GPIO1C2_SHIFT);
68 writel(0xffff57f5, &grf->gpio1b_drv);
69}
70
71static void pinctrl_rv1108_sfc_config(struct rv1108_grf *grf)
72{
73 rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A3_MASK | GPIO2A2_MASK |
74 GPIO2A1_MASK | GPIO2A0_MASK,
75 GPIO2A3_SFC_HOLD_IO3 << GPIO2A3_SHIFT |
76 GPIO2A2_SFC_WP_IO2 << GPIO2A2_SHIFT |
77 GPIO2A1_SFC_SO_IO1 << GPIO2A1_SHIFT |
78 GPIO2A0_SFC_SI_IO0 << GPIO2A0_SHIFT);
79 rk_clrsetreg(&grf->gpio2b_iomux, GPIO2B7_MASK | GPIO2B4_MASK,
80 GPIO2B7_SFC_CLK << GPIO2B7_SHIFT |
81 GPIO2B4_SFC_CSN0 << GPIO2B4_SHIFT);
82}
83
84static int rv1108_pinctrl_request(struct udevice *dev, int func, int flags)
85{
86 struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
87
88 switch (func) {
89 case PERIPH_ID_UART0:
90 case PERIPH_ID_UART1:
91 case PERIPH_ID_UART2:
92 pinctrl_rv1108_uart_config(priv->grf, func);
93 break;
94 case PERIPH_ID_GMAC:
95 pinctrl_rv1108_gmac_config(priv->grf, func);
96 case PERIPH_ID_SFC:
97 pinctrl_rv1108_sfc_config(priv->grf);
98 default:
99 return -EINVAL;
100 }
101
102 return 0;
103}
104
105static int rv1108_pinctrl_get_periph_id(struct udevice *dev,
106 struct udevice *periph)
107{
108 u32 cell[3];
109 int ret;
110
Philipp Tomsichff7865f2017-06-07 18:45:57 +0200[diff] [blame]111 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
Andy Yan96c3da92017-06-01 18:00:10 +0800[diff] [blame]112 if (ret < 0)
113 return -EINVAL;
114
115 switch (cell[1]) {
116 case 11:
117 return PERIPH_ID_SDCARD;
118 case 13:
119 return PERIPH_ID_EMMC;
120 case 19:
121 return PERIPH_ID_GMAC;
122 case 30:
123 return PERIPH_ID_I2C0;
124 case 31:
125 return PERIPH_ID_I2C1;
126 case 32:
127 return PERIPH_ID_I2C2;
128 case 39:
129 return PERIPH_ID_PWM0;
130 case 44:
131 return PERIPH_ID_UART0;
132 case 45:
133 return PERIPH_ID_UART1;
134 case 46:
135 return PERIPH_ID_UART2;
136 case 56:
137 return PERIPH_ID_SFC;
138 }
139
140 return -ENOENT;
141}
142
143static int rv1108_pinctrl_set_state_simple(struct udevice *dev,
144 struct udevice *periph)
145{
146 int func;
147
148 func = rv1108_pinctrl_get_periph_id(dev, periph);
149 if (func < 0)
150 return func;
151
152 return rv1108_pinctrl_request(dev, func, 0);
153}
154
155static struct pinctrl_ops rv1108_pinctrl_ops = {
156 .set_state_simple = rv1108_pinctrl_set_state_simple,
157 .request = rv1108_pinctrl_request,
158 .get_periph_id = rv1108_pinctrl_get_periph_id,
159};
160
161static int rv1108_pinctrl_probe(struct udevice *dev)
162{
163 struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
164
165 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
166
167 return 0;
168}
169
170static const struct udevice_id rv1108_pinctrl_ids[] = {
171 {.compatible = "rockchip,rv1108-pinctrl" },
172 { }
173};
174
175U_BOOT_DRIVER(pinctrl_rv1108) = {
176 .name = "pinctrl_rv1108",
177 .id = UCLASS_PINCTRL,
178 .of_match = rv1108_pinctrl_ids,
179 .priv_auto_alloc_size = sizeof(struct rv1108_pinctrl_priv),
180 .ops = &rv1108_pinctrl_ops,
181 .bind = dm_scan_fdt_dev,
182 .probe = rv1108_pinctrl_probe,
183};