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trem0053e3c2013-09-10 22:08:39 +02001/*
2 *
3 * Configuration settings for the Armadeus Project motherboard APF27
4 *
5 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_VERSION_VARIABLE
14#define CONFIG_ENV_VERSION 10
15#define CONFIG_IDENT_STRING " apf27 patch 3.10"
16#define CONFIG_BOARD_NAME apf27
17
18/*
19 * SoC configurations
20 */
Masahiro Yamada4fb5d072014-11-06 14:59:36 +090021#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
trem0053e3c2013-09-10 22:08:39 +020022#define CONFIG_MACH_TYPE 1698 /* APF27 */
trem0053e3c2013-09-10 22:08:39 +020023
24/*
25 * Enable the call to miscellaneous platform dependent initialization.
26 */
Joe Hershberger5a9d7f12015-06-22 16:15:30 -050027#define CONFIG_SYS_NO_FLASH
trem0053e3c2013-09-10 22:08:39 +020028
29/*
30 * Board display option
31 */
32#define CONFIG_DISPLAY_BOARDINFO
33#define CONFIG_DISPLAY_CPUINFO
34
35/*
36 * SPL
37 */
trem0053e3c2013-09-10 22:08:39 +020038#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
39#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
40#define CONFIG_SPL_MAX_SIZE 2048
41#define CONFIG_SPL_TEXT_BASE 0xA0000000
Heiko Schocher62cb1562015-06-29 09:10:46 +020042#define CONFIG_SPL_SERIAL_SUPPORT
trem0053e3c2013-09-10 22:08:39 +020043
44/* NAND boot config */
45#define CONFIG_SPL_NAND_SUPPORT
46#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
47#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
48#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
49#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
50
51/*
52 * BOOTP options
53 */
54#define CONFIG_BOOTP_SUBNETMASK
55#define CONFIG_BOOTP_GATEWAY
56#define CONFIG_BOOTP_HOSTNAME
57#define CONFIG_BOOTP_BOOTPATH
58#define CONFIG_BOOTP_BOOTFILESIZE
59#define CONFIG_BOOTP_DNS
60#define CONFIG_BOOTP_DNS2
61
62#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
63#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
64
65/*
66 * U-Boot Commands
67 */
trem0053e3c2013-09-10 22:08:39 +020068#define CONFIG_CMD_BSP /* Board Specific functions */
trem0053e3c2013-09-10 22:08:39 +020069#define CONFIG_CMD_DATE
trem0053e3c2013-09-10 22:08:39 +020070#define CONFIG_CMD_EEPROM
trem0053e3c2013-09-10 22:08:39 +020071#define CONFIG_CMD_IMX_FUSE /* imx iim fuse */
trem0053e3c2013-09-10 22:08:39 +020072#define CONFIG_CMD_MTDPARTS /* MTD partition support */
73#define CONFIG_CMD_NAND /* NAND support */
74#define CONFIG_CMD_NAND_LOCK_UNLOCK
75#define CONFIG_CMD_NAND_TRIMFFS
trem0053e3c2013-09-10 22:08:39 +020076#define CONFIG_CMD_UBI
77#define CONFIG_CMD_UBIFS
78
79/*
80 * Memory configurations
81 */
82#define CONFIG_NR_DRAM_POPULATED 1
83#define CONFIG_NR_DRAM_BANKS 2
84
85#define ACFG_SDRAM_MBYTE_SYZE 64
86
87#define PHYS_SDRAM_1 0xA0000000
88#define PHYS_SDRAM_2 0xB0000000
89#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
90#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
91#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
92#define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
93
94#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
95 + PHYS_SDRAM_1_SIZE - 0x0100000)
96
97#define CONFIG_SYS_TEXT_BASE 0xA0000800
98
99/*
100 * FLASH organization
101 */
102#define ACFG_MONITOR_OFFSET 0x00000000
103#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
104#define CONFIG_ENV_IS_IN_NAND
105#define CONFIG_ENV_OVERWRITE
106#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
107#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
108#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
109#define CONFIG_ENV_OFFSET_REDUND \
110 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */
111#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */
112#define CONFIG_FIRMWARE_OFFSET 0x00200000
113#define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */
114#define CONFIG_KERNEL_OFFSET 0x00300000
115#define CONFIG_ROOTFS_OFFSET 0x00800000
116
117#define CONFIG_MTDMAP "mxc_nand.0"
118#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
119#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \
120 ":1M(u-boot)ro," \
121 "512K(env)," \
122 "512K(env2)," \
123 "512K(firmware)," \
124 "512K(dtb)," \
125 "5M(kernel)," \
126 "-(rootfs)"
127
128/*
129 * U-Boot general configurations
130 */
131#define CONFIG_SYS_LONGHELP
trem0053e3c2013-09-10 22:08:39 +0200132#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
133#define CONFIG_SYS_PBSIZE \
134 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
135 /* Print buffer size */
136#define CONFIG_SYS_MAXARGS 16 /* max command args */
137#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
138 /* Boot argument buffer size */
139#define CONFIG_AUTO_COMPLETE
140#define CONFIG_CMDLINE_EDITING
trem0053e3c2013-09-10 22:08:39 +0200141#define CONFIG_ENV_VARS_UBOOT_CONFIG
142#define CONFIG_PREBOOT "run check_flash check_env;"
143
trem0053e3c2013-09-10 22:08:39 +0200144/*
145 * Boot Linux
146 */
147#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
148#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
149#define CONFIG_INITRD_TAG /* send initrd params */
150
trem0053e3c2013-09-10 22:08:39 +0200151#define CONFIG_BOOTDELAY 5
152#define CONFIG_ZERO_BOOTDELAY_CHECK
153#define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin"
154#define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," \
155 __stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
156 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
157
158#define ACFG_CONSOLE_DEV ttySMX0
159#define CONFIG_BOOTCOMMAND "run ubifsboot"
160#define CONFIG_SYS_AUTOLOAD "no"
161/*
162 * Default load address for user programs and kernel
163 */
164#define CONFIG_LOADADDR 0xA0000000
165#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
166
167/*
168 * Extra Environments
169 */
170#define CONFIG_EXTRA_ENV_SETTINGS \
171 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
172 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \
173 "mtdparts=" MTDPARTS_DEFAULT "\0" \
174 "partition=nand0,6\0" \
175 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \
176 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \
177 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \
178 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \
179 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
180 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
181 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
182 "kernel_addr_r=A0000000\0" \
183 "check_env=if test -n ${flash_env_version}; " \
184 "then env default env_version; " \
185 "else env set flash_env_version ${env_version}; env save; "\
186 "fi; " \
187 "if itest ${flash_env_version} < ${env_version}; then " \
188 "echo \"*** Warning - Environment version" \
189 " change suggests: run flash_reset_env; reset\"; "\
190 "env default flash_reset_env; "\
191 "fi; \0" \
192 "check_flash=nand lock; nand unlock ${env_addr}; \0" \
193 "flash_reset_env=env default -f -a; saveenv; run update_env;" \
194 "echo Flash environment variables erased!\0" \
195 "download_uboot=tftpboot ${loadaddr} ${board_name}" \
196 "-u-boot-with-spl.bin\0" \
197 "flash_uboot=nand unlock ${u-boot_addr} ;" \
198 "nand erase.part u-boot;" \
199 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
200 "then nand lock; nand unlock ${env_addr};" \
201 "echo Flashing of uboot succeed;" \
202 "else echo Flashing of uboot failed;" \
203 "fi; \0" \
204 "update_uboot=run download_uboot flash_uboot\0" \
205 "download_env=tftpboot ${loadaddr} ${board_name}" \
206 "-u-boot-env.txt\0" \
207 "flash_env=env import -t ${loadaddr}; env save; \0" \
208 "update_env=run download_env flash_env\0" \
209 "update_all=run update_env update_uboot\0" \
210 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \
211
212/*
213 * Serial Driver
214 */
215#define CONFIG_MXC_UART
216#define CONFIG_CONS_INDEX 1
217#define CONFIG_BAUDRATE 115200
218#define CONFIG_MXC_UART_BASE UART1_BASE
219
220/*
221 * GPIO
222 */
223#define CONFIG_MXC_GPIO
224
225/*
226 * NOR
227 */
228
229/*
230 * NAND
231 */
232#define CONFIG_NAND_MXC
233
234#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
235#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
236#define CONFIG_SYS_MAX_NAND_DEVICE 1
237
238#define CONFIG_MXC_NAND_HWECC
239#define CONFIG_SYS_NAND_LARGEPAGE
240#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
241#define CONFIG_SYS_NAND_PAGE_SIZE 2048
242#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
243#define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \
244 CONFIG_SYS_NAND_PAGE_SIZE
245#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
246#define CONFIG_SYS_NAND_BAD_BLOCK_POS 11
247#define NAND_MAX_CHIPS 1
248
249#define CONFIG_FLASH_SHOW_PROGRESS 45
250#define CONFIG_SYS_NAND_QUIET 1
251
252/*
253 * Partitions & Filsystems
254 */
255#define CONFIG_MTD_DEVICE
256#define CONFIG_MTD_PARTITIONS
257#define CONFIG_DOS_PARTITION
258#define CONFIG_SUPPORT_VFAT
259
260/*
261 * UBIFS
262 */
263#define CONFIG_RBTREE
264#define CONFIG_LZO
265
266/*
267 * Ethernet (on SOC imx FEC)
268 */
269#define CONFIG_FEC_MXC
270#define CONFIG_FEC_MXC_PHYADDR 0x1f
271#define CONFIG_MII /* MII PHY management */
272
273/*
trem97852892013-09-10 22:08:40 +0200274 * FPGA
275 */
276#ifndef CONFIG_SPL_BUILD
277#define CONFIG_FPGA
278#endif
279#define CONFIG_FPGA_COUNT 1
280#define CONFIG_FPGA_XILINX
281#define CONFIG_FPGA_SPARTAN3
282#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
283#define CONFIG_SYS_FPGA_PROG_FEEDBACK
284#define CONFIG_SYS_FPGA_CHECK_CTRLC
285#define CONFIG_SYS_FPGA_CHECK_ERROR
286
287/*
trem0053e3c2013-09-10 22:08:39 +0200288 * Fuses - IIM
289 */
290#ifdef CONFIG_CMD_IMX_FUSE
291#define IIM_MAC_BANK 0
292#define IIM_MAC_ROW 5
293#define IIM0_SCC_KEY 11
294#define IIM1_SUID 1
295#endif
296
297/*
298 * I2C
299 */
300
301#ifdef CONFIG_CMD_I2C
trem03997412013-09-21 18:13:36 +0200302#define CONFIG_SYS_I2C
303#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +0200304#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
305#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
trem03997412013-09-21 18:13:36 +0200306#define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
307#define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
308#define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
309#define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F
trem0053e3c2013-09-10 22:08:39 +0200310#define CONFIG_SYS_I2C_NOPROBES { }
311
312#ifdef CONFIG_CMD_EEPROM
313# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
314# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
315#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
316#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
317#endif /* CONFIG_CMD_EEPROM */
318#endif /* CONFIG_CMD_I2C */
319
320/*
321 * SD/MMC
322 */
323#ifdef CONFIG_CMD_MMC
324#define CONFIG_MMC
325#define CONFIG_GENERIC_MMC
326#define CONFIG_MXC_MMC
327#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
328#endif
329
330/*
331 * RTC
332 */
333#ifdef CONFIG_CMD_DATE
334#define CONFIG_RTC_DS1374
335#define CONFIG_SYS_RTC_BUS_NUM 0
336#endif /* CONFIG_CMD_DATE */
337
338/*
trem0053e3c2013-09-10 22:08:39 +0200339 * PLL
340 *
341 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
342 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
343 */
344#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
345
346#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
347/* micron 64MB */
348#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
349#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
350#endif
351
352#if (ACFG_SDRAM_MBYTE_SYZE == 128)
353/* micron 128MB */
354#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
355#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
356#endif
357
358#if (ACFG_SDRAM_MBYTE_SYZE == 256)
359/* micron 256MB */
360#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
361#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
362#endif
363
364#endif /* __CONFIG_H */