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Sonic Zhang02bab342008-11-26 22:16:45 -05001/*
2 * Driver for Blackfin on-chip ATAPI controller.
3 *
4 * Enter bugs at http://blackfin.uclinux.org/
5 *
6 * Copyright (c) 2008 Analog Devices Inc.
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#include <common.h>
12#include <command.h>
13#include <config.h>
14#include <asm/byteorder.h>
15#include <asm/io.h>
16#include <asm/errno.h>
Mike Frysinger6d23f582010-06-02 06:00:04 -040017#include <asm/portmux.h>
Sonic Zhang02bab342008-11-26 22:16:45 -050018#include <asm/mach-common/bits/pata.h>
19#include <ata.h>
Pavel Herrmann9e9f6282012-09-27 23:18:04 +000020#include <sata.h>
Sonic Zhang02bab342008-11-26 22:16:45 -050021#include <libata.h>
22#include "pata_bfin.h"
23
24static struct ata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
25
26/**
27 * PIO Mode - Frequency compatibility
28 */
29/* mode: 0 1 2 3 4 */
30static const u32 pio_fsclk[] =
31{ 33333333, 33333333, 33333333, 33333333, 33333333 };
32
33/**
34 * MDMA Mode - Frequency compatibility
35 */
36/* mode: 0 1 2 */
37static const u32 mdma_fsclk[] = { 33333333, 33333333, 33333333 };
38
39/**
40 * UDMA Mode - Frequency compatibility
41 *
42 * UDMA5 - 100 MB/s - SCLK = 133 MHz
43 * UDMA4 - 66 MB/s - SCLK >= 80 MHz
44 * UDMA3 - 44.4 MB/s - SCLK >= 50 MHz
45 * UDMA2 - 33 MB/s - SCLK >= 40 MHz
46 */
47/* mode: 0 1 2 3 4 5 */
48static const u32 udma_fsclk[] =
49{ 33333333, 33333333, 40000000, 50000000, 80000000, 133333333 };
50
51/**
52 * Register transfer timing table
53 */
54/* mode: 0 1 2 3 4 */
55/* Cycle Time */
56static const u32 reg_t0min[] = { 600, 383, 330, 180, 120 };
57/* DIOR/DIOW to end cycle */
58static const u32 reg_t2min[] = { 290, 290, 290, 70, 25 };
59/* DIOR/DIOW asserted pulse width */
60static const u32 reg_teocmin[] = { 290, 290, 290, 80, 70 };
61
62/**
63 * PIO timing table
64 */
65/* mode: 0 1 2 3 4 */
66/* Cycle Time */
67static const u32 pio_t0min[] = { 600, 383, 240, 180, 120 };
68/* Address valid to DIOR/DIORW */
69static const u32 pio_t1min[] = { 70, 50, 30, 30, 25 };
70/* DIOR/DIOW to end cycle */
71static const u32 pio_t2min[] = { 165, 125, 100, 80, 70 };
72/* DIOR/DIOW asserted pulse width */
73static const u32 pio_teocmin[] = { 165, 125, 100, 70, 25 };
74/* DIOW data hold */
75static const u32 pio_t4min[] = { 30, 20, 15, 10, 10 };
76
77/* ******************************************************************
78 * Multiword DMA timing table
79 * ******************************************************************
80 */
81/* mode: 0 1 2 */
82/* Cycle Time */
83static const u32 mdma_t0min[] = { 480, 150, 120 };
84/* DIOR/DIOW asserted pulse width */
85static const u32 mdma_tdmin[] = { 215, 80, 70 };
86/* DMACK to read data released */
87static const u32 mdma_thmin[] = { 20, 15, 10 };
88/* DIOR/DIOW to DMACK hold */
89static const u32 mdma_tjmin[] = { 20, 5, 5 };
90/* DIOR negated pulse width */
91static const u32 mdma_tkrmin[] = { 50, 50, 25 };
92/* DIOR negated pulse width */
93static const u32 mdma_tkwmin[] = { 215, 50, 25 };
94/* CS[1:0] valid to DIOR/DIOW */
95static const u32 mdma_tmmin[] = { 50, 30, 25 };
96/* DMACK to read data released */
97static const u32 mdma_tzmax[] = { 20, 25, 25 };
98
99/**
100 * Ultra DMA timing table
101 */
102/* mode: 0 1 2 3 4 5 */
103static const u32 udma_tcycmin[] = { 112, 73, 54, 39, 25, 17 };
104static const u32 udma_tdvsmin[] = { 70, 48, 31, 20, 7, 5 };
105static const u32 udma_tenvmax[] = { 70, 70, 70, 55, 55, 50 };
106static const u32 udma_trpmin[] = { 160, 125, 100, 100, 100, 85 };
107static const u32 udma_tmin[] = { 5, 5, 5, 5, 3, 3 };
108
109
110static const u32 udma_tmlimin = 20;
111static const u32 udma_tzahmin = 20;
112static const u32 udma_tenvmin = 20;
113static const u32 udma_tackmin = 20;
114static const u32 udma_tssmin = 50;
115
116static void msleep(int count)
117{
118 int i;
119
120 for (i = 0; i < count; i++)
121 udelay(1000);
122}
123
124/**
125 *
126 * Function: num_clocks_min
127 *
128 * Description:
129 * calculate number of SCLK cycles to meet minimum timing
130 */
131static unsigned short num_clocks_min(unsigned long tmin,
132 unsigned long fsclk)
133{
134 unsigned long tmp ;
135 unsigned short result;
136
137 tmp = tmin * (fsclk/1000/1000) / 1000;
138 result = (unsigned short)tmp;
139 if ((tmp*1000*1000) < (tmin*(fsclk/1000)))
140 result++;
141
142 return result;
143}
144
145/**
146 * bfin_set_piomode - Initialize host controller PATA PIO timings
147 * @ap: Port whose timings we are configuring
148 * @pio_mode: mode
149 *
150 * Set PIO mode for device.
151 *
152 * LOCKING:
153 * None (inherited from caller).
154 */
155
156static void bfin_set_piomode(struct ata_port *ap, int pio_mode)
157{
158 int mode = pio_mode - XFER_PIO_0;
159 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
160 unsigned int fsclk = get_sclk();
161 unsigned short teoc_reg, t2_reg, teoc_pio;
162 unsigned short t4_reg, t2_pio, t1_reg;
163 unsigned short n0, n6, t6min = 5;
164
165 /* the most restrictive timing value is t6 and tc, the DIOW - data hold
166 * If one SCLK pulse is longer than this minimum value then register
167 * transfers cannot be supported at this frequency.
168 */
169 n6 = num_clocks_min(t6min, fsclk);
170 if (mode >= 0 && mode <= 4 && n6 >= 1) {
171 debug("set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
172 /* calculate the timing values for register transfers. */
173 while (mode > 0 && pio_fsclk[mode] > fsclk)
174 mode--;
175
176 /* DIOR/DIOW to end cycle time */
177 t2_reg = num_clocks_min(reg_t2min[mode], fsclk);
178 /* DIOR/DIOW asserted pulse width */
179 teoc_reg = num_clocks_min(reg_teocmin[mode], fsclk);
180 /* Cycle Time */
181 n0 = num_clocks_min(reg_t0min[mode], fsclk);
182
183 /* increase t2 until we meed the minimum cycle length */
184 if (t2_reg + teoc_reg < n0)
185 t2_reg = n0 - teoc_reg;
186
187 /* calculate the timing values for pio transfers. */
188
189 /* DIOR/DIOW to end cycle time */
190 t2_pio = num_clocks_min(pio_t2min[mode], fsclk);
191 /* DIOR/DIOW asserted pulse width */
192 teoc_pio = num_clocks_min(pio_teocmin[mode], fsclk);
193 /* Cycle Time */
194 n0 = num_clocks_min(pio_t0min[mode], fsclk);
195
196 /* increase t2 until we meed the minimum cycle length */
197 if (t2_pio + teoc_pio < n0)
198 t2_pio = n0 - teoc_pio;
199
200 /* Address valid to DIOR/DIORW */
201 t1_reg = num_clocks_min(pio_t1min[mode], fsclk);
202
203 /* DIOW data hold */
204 t4_reg = num_clocks_min(pio_t4min[mode], fsclk);
205
206 ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg));
207 ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg));
208 ATAPI_SET_PIO_TIM_1(base, teoc_pio);
209 if (mode > 2) {
210 ATAPI_SET_CONTROL(base,
211 ATAPI_GET_CONTROL(base) | IORDY_EN);
212 } else {
213 ATAPI_SET_CONTROL(base,
214 ATAPI_GET_CONTROL(base) & ~IORDY_EN);
215 }
216
217 /* Disable host ATAPI PIO interrupts */
218 ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)
219 & ~(PIO_DONE_MASK | HOST_TERM_XFER_MASK));
220 SSYNC();
221 }
222}
223
224/**
225 *
226 * Function: wait_complete
227 *
228 * Description: Waits the interrupt from device
229 *
230 */
231static inline void wait_complete(void __iomem *base, unsigned short mask)
232{
233 unsigned short status;
234 unsigned int i = 0;
235
236 for (i = 0; i < PATA_BFIN_WAIT_TIMEOUT; i++) {
237 status = ATAPI_GET_INT_STATUS(base) & mask;
238 if (status)
239 break;
240 }
241
242 ATAPI_SET_INT_STATUS(base, mask);
243}
244
245/**
246 *
247 * Function: write_atapi_register
248 *
249 * Description: Writes to ATA Device Resgister
250 *
251 */
252
253static void write_atapi_register(void __iomem *base,
254 unsigned long ata_reg, unsigned short value)
255{
256 /* Program the ATA_DEV_TXBUF register with write data (to be
257 * written into the device).
258 */
259 ATAPI_SET_DEV_TXBUF(base, value);
260
261 /* Program the ATA_DEV_ADDR register with address of the
262 * device register (0x01 to 0x0F).
263 */
264 ATAPI_SET_DEV_ADDR(base, ata_reg);
265
266 /* Program the ATA_CTRL register with dir set to write (1)
267 */
268 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
269
270 /* ensure PIO DMA is not set */
271 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
272
273 /* and start the transfer */
274 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
275
276 /* Wait for the interrupt to indicate the end of the transfer.
277 * (We need to wait on and clear rhe ATA_DEV_INT interrupt status)
278 */
279 wait_complete(base, PIO_DONE_INT);
280}
281
282/**
283 *
284 * Function: read_atapi_register
285 *
286 *Description: Reads from ATA Device Resgister
287 *
288 */
289
290static unsigned short read_atapi_register(void __iomem *base,
291 unsigned long ata_reg)
292{
293 /* Program the ATA_DEV_ADDR register with address of the
294 * device register (0x01 to 0x0F).
295 */
296 ATAPI_SET_DEV_ADDR(base, ata_reg);
297
298 /* Program the ATA_CTRL register with dir set to read (0) and
299 */
300 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
301
302 /* ensure PIO DMA is not set */
303 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
304
305 /* and start the transfer */
306 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
307
308 /* Wait for the interrupt to indicate the end of the transfer.
309 * (PIO_DONE interrupt is set and it doesn't seem to matter
310 * that we don't clear it)
311 */
312 wait_complete(base, PIO_DONE_INT);
313
314 /* Read the ATA_DEV_RXBUF register with write data (to be
315 * written into the device).
316 */
317 return ATAPI_GET_DEV_RXBUF(base);
318}
319
320/**
321 *
322 * Function: write_atapi_register_data
323 *
324 * Description: Writes to ATA Device Resgister
325 *
326 */
327
328static void write_atapi_data(void __iomem *base,
329 int len, unsigned short *buf)
330{
331 int i;
332
333 /* Set transfer length to 1 */
334 ATAPI_SET_XFER_LEN(base, 1);
335
336 /* Program the ATA_DEV_ADDR register with address of the
337 * ATA_REG_DATA
338 */
339 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
340
341 /* Program the ATA_CTRL register with dir set to write (1)
342 */
343 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
344
345 /* ensure PIO DMA is not set */
346 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
347
348 for (i = 0; i < len; i++) {
349 /* Program the ATA_DEV_TXBUF register with write data (to be
350 * written into the device).
351 */
352 ATAPI_SET_DEV_TXBUF(base, buf[i]);
353
354 /* and start the transfer */
355 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
356
357 /* Wait for the interrupt to indicate the end of the transfer.
358 * (We need to wait on and clear rhe ATA_DEV_INT
359 * interrupt status)
360 */
361 wait_complete(base, PIO_DONE_INT);
362 }
363}
364
365/**
366 *
367 * Function: read_atapi_register_data
368 *
369 * Description: Reads from ATA Device Resgister
370 *
371 */
372
373static void read_atapi_data(void __iomem *base,
374 int len, unsigned short *buf)
375{
376 int i;
377
378 /* Set transfer length to 1 */
379 ATAPI_SET_XFER_LEN(base, 1);
380
381 /* Program the ATA_DEV_ADDR register with address of the
382 * ATA_REG_DATA
383 */
384 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
385
386 /* Program the ATA_CTRL register with dir set to read (0) and
387 */
388 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
389
390 /* ensure PIO DMA is not set */
391 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
392
393 for (i = 0; i < len; i++) {
394 /* and start the transfer */
395 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
396
397 /* Wait for the interrupt to indicate the end of the transfer.
398 * (PIO_DONE interrupt is set and it doesn't seem to matter
399 * that we don't clear it)
400 */
401 wait_complete(base, PIO_DONE_INT);
402
403 /* Read the ATA_DEV_RXBUF register with write data (to be
404 * written into the device).
405 */
406 buf[i] = ATAPI_GET_DEV_RXBUF(base);
407 }
408}
409
410/**
411 * bfin_check_status - Read device status reg & clear interrupt
412 * @ap: port where the device is
413 *
414 * Note: Original code is ata_check_status().
415 */
416
417static u8 bfin_check_status(struct ata_port *ap)
418{
419 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
420 return read_atapi_register(base, ATA_REG_STATUS);
421}
422
423/**
424 * bfin_check_altstatus - Read device alternate status reg
425 * @ap: port where the device is
426 */
427
428static u8 bfin_check_altstatus(struct ata_port *ap)
429{
430 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
431 return read_atapi_register(base, ATA_REG_ALTSTATUS);
432}
433
434/**
435 * bfin_ata_busy_wait - Wait for a port status register
436 * @ap: Port to wait for.
437 * @bits: bits that must be clear
438 * @max: number of 10uS waits to perform
439 *
440 * Waits up to max*10 microseconds for the selected bits in the port's
441 * status register to be cleared.
442 * Returns final value of status register.
443 *
444 * LOCKING:
445 * Inherited from caller.
446 */
447static inline u8 bfin_ata_busy_wait(struct ata_port *ap, unsigned int bits,
448 unsigned int max, u8 usealtstatus)
449{
450 u8 status;
451
452 do {
453 udelay(10);
454 if (usealtstatus)
455 status = bfin_check_altstatus(ap);
456 else
457 status = bfin_check_status(ap);
458 max--;
459 } while (status != 0xff && (status & bits) && (max > 0));
460
461 return status;
462}
463
464/**
465 * bfin_ata_busy_sleep - sleep until BSY clears, or timeout
466 * @ap: port containing status register to be polled
467 * @tmout_pat: impatience timeout in msecs
468 * @tmout: overall timeout in msecs
469 *
470 * Sleep until ATA Status register bit BSY clears,
471 * or a timeout occurs.
472 *
473 * RETURNS:
474 * 0 on success, -errno otherwise.
475 */
476static int bfin_ata_busy_sleep(struct ata_port *ap,
477 long tmout_pat, unsigned long tmout)
478{
479 u8 status;
480
481 status = bfin_ata_busy_wait(ap, ATA_BUSY, 300, 0);
482 while (status != 0xff && (status & ATA_BUSY) && tmout_pat > 0) {
483 msleep(50);
484 tmout_pat -= 50;
485 status = bfin_ata_busy_wait(ap, ATA_BUSY, 3, 0);
486 }
487
488 if (status != 0xff && (status & ATA_BUSY))
489 printf("port is slow to respond, please be patient "
490 "(Status 0x%x)\n", status);
491
492 while (status != 0xff && (status & ATA_BUSY) && tmout_pat > 0) {
493 msleep(50);
494 tmout_pat -= 50;
495 status = bfin_check_status(ap);
496 }
497
498 if (status == 0xff)
499 return -ENODEV;
500
501 if (status & ATA_BUSY) {
502 printf("port failed to respond "
503 "(%lu secs, Status 0x%x)\n",
504 DIV_ROUND_UP(tmout, 1000), status);
505 return -EBUSY;
506 }
507
508 return 0;
509}
510
511/**
512 * bfin_dev_select - Select device 0/1 on ATA bus
513 * @ap: ATA channel to manipulate
514 * @device: ATA device (numbered from zero) to select
515 *
516 * Note: Original code is ata_sff_dev_select().
517 */
518
519static void bfin_dev_select(struct ata_port *ap, unsigned int device)
520{
521 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
522 u8 tmp;
523
524
525 if (device == 0)
526 tmp = ATA_DEVICE_OBS;
527 else
528 tmp = ATA_DEVICE_OBS | ATA_DEV1;
529
530 write_atapi_register(base, ATA_REG_DEVICE, tmp);
531 udelay(1);
532}
533
534/**
535 * bfin_devchk - PATA device presence detection
536 * @ap: ATA channel to examine
537 * @device: Device to examine (starting at zero)
538 *
539 * Note: Original code is ata_devchk().
540 */
541
542static unsigned int bfin_devchk(struct ata_port *ap,
543 unsigned int device)
544{
545 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
546 u8 nsect, lbal;
547
548 bfin_dev_select(ap, device);
549
550 write_atapi_register(base, ATA_REG_NSECT, 0x55);
551 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
552
553 write_atapi_register(base, ATA_REG_NSECT, 0xaa);
554 write_atapi_register(base, ATA_REG_LBAL, 0x55);
555
556 write_atapi_register(base, ATA_REG_NSECT, 0x55);
557 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
558
559 nsect = read_atapi_register(base, ATA_REG_NSECT);
560 lbal = read_atapi_register(base, ATA_REG_LBAL);
561
562 if ((nsect == 0x55) && (lbal == 0xaa))
563 return 1; /* we found a device */
564
565 return 0; /* nothing found */
566}
567
568/**
569 * bfin_bus_post_reset - PATA device post reset
570 *
571 * Note: Original code is ata_bus_post_reset().
572 */
573
574static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask)
575{
576 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
577 unsigned int dev0 = devmask & (1 << 0);
578 unsigned int dev1 = devmask & (1 << 1);
579 long deadline;
580
581 /* if device 0 was found in ata_devchk, wait for its
582 * BSY bit to clear
583 */
584 if (dev0)
585 bfin_ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
586
587 /* if device 1 was found in ata_devchk, wait for
588 * register access, then wait for BSY to clear
589 */
590 deadline = ATA_TMOUT_BOOT;
591 while (dev1) {
592 u8 nsect, lbal;
593
594 bfin_dev_select(ap, 1);
595 nsect = read_atapi_register(base, ATA_REG_NSECT);
596 lbal = read_atapi_register(base, ATA_REG_LBAL);
597 if ((nsect == 1) && (lbal == 1))
598 break;
599 if (deadline <= 0) {
600 dev1 = 0;
601 break;
602 }
603 msleep(50); /* give drive a breather */
604 deadline -= 50;
605 }
606 if (dev1)
607 bfin_ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
608
609 /* is all this really necessary? */
610 bfin_dev_select(ap, 0);
611 if (dev1)
612 bfin_dev_select(ap, 1);
613 if (dev0)
614 bfin_dev_select(ap, 0);
615}
616
617/**
618 * bfin_bus_softreset - PATA device software reset
619 *
620 * Note: Original code is ata_bus_softreset().
621 */
622
623static unsigned int bfin_bus_softreset(struct ata_port *ap,
624 unsigned int devmask)
625{
626 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
627
628 /* software reset. causes dev0 to be selected */
629 write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg);
630 udelay(20);
631 write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg | ATA_SRST);
632 udelay(20);
633 write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg);
634
635 /* spec mandates ">= 2ms" before checking status.
636 * We wait 150ms, because that was the magic delay used for
637 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
638 * between when the ATA command register is written, and then
639 * status is checked. Because waiting for "a while" before
640 * checking status is fine, post SRST, we perform this magic
641 * delay here as well.
642 *
643 * Old drivers/ide uses the 2mS rule and then waits for ready
644 */
645 msleep(150);
646
647 /* Before we perform post reset processing we want to see if
648 * the bus shows 0xFF because the odd clown forgets the D7
649 * pulldown resistor.
650 */
651 if (bfin_check_status(ap) == 0xFF)
652 return 0;
653
654 bfin_bus_post_reset(ap, devmask);
655
656 return 0;
657}
658
659/**
660 * bfin_softreset - reset host port via ATA SRST
661 * @ap: port to reset
662 *
663 * Note: Original code is ata_sff_softreset().
664 */
665
666static int bfin_softreset(struct ata_port *ap)
667{
668 unsigned int err_mask;
669
670 ap->dev_mask = 0;
671
672 /* determine if device 0/1 are present.
673 * only one device is supported on one port by now.
674 */
675 if (bfin_devchk(ap, 0))
676 ap->dev_mask |= (1 << 0);
677 else if (bfin_devchk(ap, 1))
678 ap->dev_mask |= (1 << 1);
679 else
680 return -ENODEV;
681
682 /* select device 0 again */
683 bfin_dev_select(ap, 0);
684
685 /* issue bus reset */
686 err_mask = bfin_bus_softreset(ap, ap->dev_mask);
687 if (err_mask) {
688 printf("SRST failed (err_mask=0x%x)\n",
689 err_mask);
690 ap->dev_mask = 0;
691 return -EIO;
692 }
693
694 return 0;
695}
696
697/**
698 * bfin_irq_clear - Clear ATAPI interrupt.
699 * @ap: Port associated with this ATA transaction.
700 *
701 * Note: Original code is ata_sff_irq_clear().
702 */
703
704static void bfin_irq_clear(struct ata_port *ap)
705{
706 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
707
708 ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
709 | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
710 | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
711}
712
713static u8 bfin_wait_for_irq(struct ata_port *ap, unsigned int max)
714{
715 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
716
717 do {
718 if (ATAPI_GET_INT_STATUS(base) & (ATAPI_DEV_INT
719 | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
720 | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT)) {
721 break;
722 }
723 udelay(1000);
724 max--;
725 } while ((max > 0));
726
727 return max == 0;
728}
729
730/**
731 * bfin_ata_reset_port - initialize BFIN ATAPI port.
732 */
733
734static int bfin_ata_reset_port(struct ata_port *ap)
735{
736 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
737 int count;
738 unsigned short status;
739
740 /* Disable all ATAPI interrupts */
741 ATAPI_SET_INT_MASK(base, 0);
742 SSYNC();
743
744 /* Assert the RESET signal 25us*/
745 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST);
746 udelay(30);
747
748 /* Negate the RESET signal for 2ms*/
749 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST);
750 msleep(2);
751
752 /* Wait on Busy flag to clear */
753 count = 10000000;
754 do {
755 status = read_atapi_register(base, ATA_REG_STATUS);
756 } while (--count && (status & ATA_BUSY));
757
758 /* Enable only ATAPI Device interrupt */
759 ATAPI_SET_INT_MASK(base, 1);
760 SSYNC();
761
762 return !count;
763}
764
765/**
766 *
767 * Function: bfin_config_atapi_gpio
768 *
769 * Description: Configures the ATAPI pins for use
770 *
771 */
772static int bfin_config_atapi_gpio(struct ata_port *ap)
773{
Mike Frysinger6d23f582010-06-02 06:00:04 -0400774 const unsigned short pins[] = {
775 P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0,
776 P_ATAPI_CS1, P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ,
777 P_ATAPI_IORDY, P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A,
778 P_ATAPI_D3A, P_ATAPI_D4A, P_ATAPI_D5A, P_ATAPI_D6A,
779 P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, P_ATAPI_D10A,
780 P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A,
781 P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, 0,
782 };
Sonic Zhang02bab342008-11-26 22:16:45 -0500783
Mike Frysinger6d23f582010-06-02 06:00:04 -0400784 peripheral_request_list(pins, "pata_bfin");
Sonic Zhang02bab342008-11-26 22:16:45 -0500785
786 return 0;
787}
788
789/**
790 * bfin_atapi_probe - attach a bfin atapi interface
791 * @pdev: platform device
792 *
793 * Register a bfin atapi interface.
794 *
795 *
796 * Platform devices are expected to contain 2 resources per port:
797 *
798 * - I/O Base (IORESOURCE_IO)
799 * - IRQ (IORESOURCE_IRQ)
800 *
801 */
802static int bfin_ata_probe_port(struct ata_port *ap)
803{
804 if (bfin_config_atapi_gpio(ap)) {
805 printf("Requesting Peripherals faild\n");
806 return -EFAULT;
807 }
808
809 if (bfin_ata_reset_port(ap)) {
810 printf("Fail to reset ATAPI device\n");
811 return -EFAULT;
812 }
813
814 if (ap->ata_mode >= XFER_PIO_0 && ap->ata_mode <= XFER_PIO_4)
815 bfin_set_piomode(ap, ap->ata_mode);
816 else {
817 printf("Given ATA data transfer mode is not supported.\n");
818 return -EFAULT;
819 }
820
821 return 0;
822}
823
824#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
825
826static void bfin_ata_identify(struct ata_port *ap, int dev)
827{
828 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
829 u8 status = 0;
830 static u16 iobuf[ATA_SECTOR_WORDS];
831 u64 n_sectors = 0;
832 hd_driveid_t *iop = (hd_driveid_t *)iobuf;
833
834 memset(iobuf, 0, sizeof(iobuf));
835
836 if (!(ap->dev_mask & (1 << dev)))
837 return;
838
839 debug("port=%d dev=%d\n", ap->port_no, dev);
840
841 bfin_dev_select(ap, dev);
842
843 status = 0;
844 /* Device Identify Command */
845 write_atapi_register(base, ATA_REG_CMD, ATA_CMD_ID_ATA);
846 bfin_check_altstatus(ap);
847 udelay(10);
848
849 status = bfin_ata_busy_wait(ap, ATA_BUSY, 1000, 0);
850 if (status & ATA_ERR) {
851 printf("\ndevice not responding\n");
852 ap->dev_mask &= ~(1 << dev);
853 return;
854 }
855
856 read_atapi_data(base, ATA_SECTOR_WORDS, iobuf);
857
858 ata_swap_buf_le16(iobuf, ATA_SECTOR_WORDS);
859
860 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
861 if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
862 printf("ata%u: no dma/lba\n", ap->port_no);
863
864#ifdef DEBUG
865 ata_dump_id(iobuf);
866#endif
867
868 n_sectors = ata_id_n_sectors(iobuf);
869
870 if (n_sectors == 0) {
871 ap->dev_mask &= ~(1 << dev);
872 return;
873 }
874
875 ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].revision,
876 ATA_ID_FW_REV, sizeof(sata_dev_desc[ap->port_no].revision));
877 ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].vendor,
878 ATA_ID_PROD, sizeof(sata_dev_desc[ap->port_no].vendor));
879 ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].product,
880 ATA_ID_SERNO, sizeof(sata_dev_desc[ap->port_no].product));
881
882 if ((iop->config & 0x0080) == 0x0080)
883 sata_dev_desc[ap->port_no].removable = 1;
884 else
885 sata_dev_desc[ap->port_no].removable = 0;
886
887 sata_dev_desc[ap->port_no].lba = (u32) n_sectors;
Mike Frysinger60ecb1b2012-02-03 08:04:22 -0500888 debug("lba=0x%lx\n", sata_dev_desc[ap->port_no].lba);
Sonic Zhang02bab342008-11-26 22:16:45 -0500889
890#ifdef CONFIG_LBA48
891 if (iop->command_set_2 & 0x0400)
892 sata_dev_desc[ap->port_no].lba48 = 1;
893 else
894 sata_dev_desc[ap->port_no].lba48 = 0;
895#endif
896
897 /* assuming HD */
898 sata_dev_desc[ap->port_no].type = DEV_TYPE_HARDDISK;
899 sata_dev_desc[ap->port_no].blksz = ATA_SECT_SIZE;
Egbert Eich2eec2ab2013-04-09 21:11:56 +0000900 sata_dev_desc[ap->port_no].log2blksz =
901 LOG2(sata_dev_desc[ap->port_no].blksz);
Sonic Zhang02bab342008-11-26 22:16:45 -0500902 sata_dev_desc[ap->port_no].lun = 0; /* just to fill something in... */
903
904 printf("PATA device#%d %s is found on ata port#%d.\n",
905 ap->port_no%PATA_DEV_NUM_PER_PORT,
906 sata_dev_desc[ap->port_no].vendor,
907 ap->port_no/PATA_DEV_NUM_PER_PORT);
908}
909
910static void bfin_ata_set_Feature_cmd(struct ata_port *ap, int dev)
911{
912 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
913 u8 status = 0;
914
915 if (!(ap->dev_mask & (1 << dev)))
916 return;
917
918 bfin_dev_select(ap, dev);
919
920 write_atapi_register(base, ATA_REG_FEATURE, SETFEATURES_XFER);
921 write_atapi_register(base, ATA_REG_NSECT, ap->ata_mode);
922 write_atapi_register(base, ATA_REG_LBAL, 0);
923 write_atapi_register(base, ATA_REG_LBAM, 0);
924 write_atapi_register(base, ATA_REG_LBAH, 0);
925
926 write_atapi_register(base, ATA_REG_DEVICE, ATA_DEVICE_OBS);
927 write_atapi_register(base, ATA_REG_CMD, ATA_CMD_SET_FEATURES);
928
929 udelay(50);
930 msleep(150);
931
932 status = bfin_ata_busy_wait(ap, ATA_BUSY, 5000, 0);
933 if ((status & (ATA_BUSY | ATA_ERR))) {
934 printf("Error : status 0x%02x\n", status);
935 ap->dev_mask &= ~(1 << dev);
936 }
937}
938
939int scan_sata(int dev)
940{
941 /* dev is the index of each ata device in the system. one PATA port
942 * contains 2 devices. one element in scan_done array indicates one
943 * PATA port. device connected to one PATA port is selected by
944 * bfin_dev_select() before access.
945 */
946 struct ata_port *ap = &port[dev];
947 static int scan_done[(CONFIG_SYS_SATA_MAX_DEVICE+1)/PATA_DEV_NUM_PER_PORT];
948
949 if (scan_done[dev/PATA_DEV_NUM_PER_PORT])
950 return 0;
951
952 /* Check for attached device */
953 if (!bfin_ata_probe_port(ap)) {
954 if (bfin_softreset(ap)) {
955 /* soft reset failed, try a hard one */
956 bfin_ata_reset_port(ap);
957 if (bfin_softreset(ap))
958 scan_done[dev/PATA_DEV_NUM_PER_PORT] = 1;
959 } else {
960 scan_done[dev/PATA_DEV_NUM_PER_PORT] = 1;
961 }
962 }
963 if (scan_done[dev/PATA_DEV_NUM_PER_PORT]) {
964 /* Probe device and set xfer mode */
965 bfin_ata_identify(ap, dev%PATA_DEV_NUM_PER_PORT);
966 bfin_ata_set_Feature_cmd(ap, dev%PATA_DEV_NUM_PER_PORT);
967 init_part(&sata_dev_desc[dev]);
968 return 0;
969 }
970
971 printf("PATA device#%d is not present on ATA port#%d.\n",
972 ap->port_no%PATA_DEV_NUM_PER_PORT,
973 ap->port_no/PATA_DEV_NUM_PER_PORT);
974
975 return -1;
976}
977
978int init_sata(int dev)
979{
980 struct ata_port *ap = &port[dev];
981 static u8 init_done;
982 int res = 1;
983
984 if (init_done)
985 return res;
986
987 init_done = 1;
988
989 switch (dev/PATA_DEV_NUM_PER_PORT) {
990 case 0:
991 ap->ioaddr.ctl_addr = ATAPI_CONTROL;
992 ap->ata_mode = CONFIG_BFIN_ATA_MODE;
993 break;
994 default:
995 printf("Tried to scan unknown port %d.\n", dev);
996 return res;
997 }
998
999 if (ap->ata_mode < XFER_PIO_0 || ap->ata_mode > XFER_PIO_4) {
1000 ap->ata_mode = XFER_PIO_4;
1001 printf("DMA mode is not supported. Set to PIO mode 4.\n");
1002 }
1003
1004 ap->port_no = dev;
1005 ap->ctl_reg = 0x8; /*Default value of control reg */
1006
1007 res = 0;
1008 return res;
1009}
1010
1011/* Read up to 255 sectors
1012 *
1013 * Returns sectors read
1014*/
1015static u8 do_one_read(struct ata_port *ap, u64 blknr, u8 blkcnt, u16 *buffer,
1016 uchar lba48)
1017{
1018 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1019 u8 sr = 0;
1020 u8 status;
1021 u16 err = 0;
1022
1023 if (!(bfin_check_status(ap) & ATA_DRDY)) {
1024 printf("Device ata%d not ready\n", ap->port_no);
1025 return 0;
1026 }
1027
1028 /* Set up transfer */
1029#ifdef CONFIG_LBA48
1030 if (lba48) {
1031 /* write high bits */
1032 write_atapi_register(base, ATA_REG_NSECT, 0);
1033 write_atapi_register(base, ATA_REG_LBAL, (blknr >> 24) & 0xFF);
1034 write_atapi_register(base, ATA_REG_LBAM, (blknr >> 32) & 0xFF);
1035 write_atapi_register(base, ATA_REG_LBAH, (blknr >> 40) & 0xFF);
1036 }
1037#endif
1038 write_atapi_register(base, ATA_REG_NSECT, blkcnt);
1039 write_atapi_register(base, ATA_REG_LBAL, (blknr >> 0) & 0xFF);
1040 write_atapi_register(base, ATA_REG_LBAM, (blknr >> 8) & 0xFF);
1041 write_atapi_register(base, ATA_REG_LBAH, (blknr >> 16) & 0xFF);
1042
1043#ifdef CONFIG_LBA48
1044 if (lba48) {
1045 write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA);
1046 write_atapi_register(base, ATA_REG_CMD, ATA_CMD_PIO_READ_EXT);
1047 } else
1048#endif
1049 {
1050 write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA | ((blknr >> 24) & 0xF));
1051 write_atapi_register(base, ATA_REG_CMD, ATA_CMD_PIO_READ);
1052 }
1053 status = bfin_ata_busy_wait(ap, ATA_BUSY, 500000, 1);
1054
1055 if (status & (ATA_BUSY | ATA_ERR)) {
1056 printf("Device %d not responding status 0x%x.\n", ap->port_no, status);
1057 err = read_atapi_register(base, ATA_REG_ERR);
1058 printf("Error reg = 0x%x\n", err);
1059 return sr;
1060 }
1061
1062 while (blkcnt--) {
1063 if (bfin_wait_for_irq(ap, 500)) {
1064 printf("ata%u irq failed\n", ap->port_no);
1065 return sr;
1066 }
1067
1068 status = bfin_check_status(ap);
1069 if (status & ATA_ERR) {
1070 err = read_atapi_register(base, ATA_REG_ERR);
1071 printf("ata%u error %d\n", ap->port_no, err);
1072 return sr;
1073 }
1074 bfin_irq_clear(ap);
1075
1076 /* Read one sector */
1077 read_atapi_data(base, ATA_SECTOR_WORDS, buffer);
1078 buffer += ATA_SECTOR_WORDS;
1079 sr++;
1080 }
1081
1082 return sr;
1083}
1084
Tom Rini9ee1aa72012-09-29 07:56:31 -07001085ulong sata_read(int dev, ulong block, lbaint_t blkcnt, void *buff)
Sonic Zhang02bab342008-11-26 22:16:45 -05001086{
1087 struct ata_port *ap = &port[dev];
1088 ulong n = 0, sread;
1089 u16 *buffer = (u16 *) buff;
1090 u8 status = 0;
1091 u64 blknr = (u64) block;
1092 unsigned char lba48 = 0;
1093
1094#ifdef CONFIG_LBA48
1095 if (blknr > 0xfffffff) {
1096 if (!sata_dev_desc[dev].lba48) {
1097 printf("Drive doesn't support 48-bit addressing\n");
1098 return 0;
1099 }
1100 /* more than 28 bits used, use 48bit mode */
1101 lba48 = 1;
1102 }
1103#endif
1104 bfin_dev_select(ap, dev%PATA_DEV_NUM_PER_PORT);
1105
1106 while (blkcnt > 0) {
1107
1108 if (blkcnt > 255)
1109 sread = 255;
1110 else
1111 sread = blkcnt;
1112
1113 status = do_one_read(ap, blknr, sread, buffer, lba48);
1114 if (status != sread) {
1115 printf("Read failed\n");
1116 return n;
1117 }
1118
1119 blkcnt -= sread;
1120 blknr += sread;
1121 n += sread;
1122 buffer += sread * ATA_SECTOR_WORDS;
1123 }
1124 return n;
1125}
1126
Tom Rini9ee1aa72012-09-29 07:56:31 -07001127ulong sata_write(int dev, ulong block, lbaint_t blkcnt, const void *buff)
Sonic Zhang02bab342008-11-26 22:16:45 -05001128{
1129 struct ata_port *ap = &port[dev];
1130 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1131 ulong n = 0;
1132 u16 *buffer = (u16 *) buff;
1133 unsigned char status = 0;
1134 u64 blknr = (u64) block;
1135#ifdef CONFIG_LBA48
1136 unsigned char lba48 = 0;
1137
1138 if (blknr > 0xfffffff) {
1139 if (!sata_dev_desc[dev].lba48) {
1140 printf("Drive doesn't support 48-bit addressing\n");
1141 return 0;
1142 }
1143 /* more than 28 bits used, use 48bit mode */
1144 lba48 = 1;
1145 }
1146#endif
1147
1148 bfin_dev_select(ap, dev%PATA_DEV_NUM_PER_PORT);
1149
1150 while (blkcnt-- > 0) {
1151 status = bfin_ata_busy_wait(ap, ATA_BUSY, 50000, 0);
1152 if (status & ATA_BUSY) {
1153 printf("ata%u failed to respond\n", ap->port_no);
1154 return n;
1155 }
1156#ifdef CONFIG_LBA48
1157 if (lba48) {
1158 /* write high bits */
1159 write_atapi_register(base, ATA_REG_NSECT, 0);
1160 write_atapi_register(base, ATA_REG_LBAL,
1161 (blknr >> 24) & 0xFF);
1162 write_atapi_register(base, ATA_REG_LBAM,
1163 (blknr >> 32) & 0xFF);
1164 write_atapi_register(base, ATA_REG_LBAH,
1165 (blknr >> 40) & 0xFF);
1166 }
1167#endif
1168 write_atapi_register(base, ATA_REG_NSECT, 1);
1169 write_atapi_register(base, ATA_REG_LBAL, (blknr >> 0) & 0xFF);
1170 write_atapi_register(base, ATA_REG_LBAM, (blknr >> 8) & 0xFF);
1171 write_atapi_register(base, ATA_REG_LBAH, (blknr >> 16) & 0xFF);
1172#ifdef CONFIG_LBA48
1173 if (lba48) {
1174 write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA);
1175 write_atapi_register(base, ATA_REG_CMD,
1176 ATA_CMD_PIO_WRITE_EXT);
1177 } else
1178#endif
1179 {
1180 write_atapi_register(base, ATA_REG_DEVICE,
1181 ATA_LBA | ((blknr >> 24) & 0xF));
1182 write_atapi_register(base, ATA_REG_CMD,
1183 ATA_CMD_PIO_WRITE);
1184 }
1185
1186 /*may take up to 5 sec */
1187 status = bfin_ata_busy_wait(ap, ATA_BUSY, 50000, 0);
1188 if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
1189 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
1190 ap->port_no, (ulong) blknr, status);
1191 return n;
1192 }
1193
1194 write_atapi_data(base, ATA_SECTOR_WORDS, buffer);
1195 bfin_check_altstatus(ap);
1196 udelay(1);
1197
1198 ++n;
1199 ++blknr;
1200 buffer += ATA_SECTOR_WORDS;
1201 }
1202 return n;
1203}