blob: a33cf1d408deb078922ec654d1be009ae6d1d6cb [file] [log] [blame]
Alexey Brodkinc15be5b2018-01-24 21:37:14 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
4 */
5/dts-v1/;
6
7#include "skeleton.dtsi"
8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 aliases {
14 console = &uart0;
15 };
16
17 cpu_card {
18 core_clk: core_clk {
19 #clock-cells = <0>;
20 compatible = "fixed-clock";
21 clock-frequency = <144000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -070022 bootph-all;
Alexey Brodkinc15be5b2018-01-24 21:37:14 +030023 };
24 };
25
26 uart0: serial0@80014000 {
27 compatible = "snps,dw-apb-uart";
28 clock-frequency = <16000000>;
29 reg = <0x80014000 0x1000>;
30 reg-shift = <2>;
31 reg-io-width = <4>;
32 };
33
34 usb: usb@f0040000 {
35 compatible = "snps,dwc2";
36 reg = <0xf0040000 0x10000>;
37 phys = <&usbphy>;
38 phy-names = "usb2-phy";
39 };
40
41 usbphy: phy {
Marek Vasute0114102021-03-31 11:23:36 +020042 compatible = "usb-nop-xceiv";
Alexey Brodkinc15be5b2018-01-24 21:37:14 +030043 #phy-cells = <0>;
44 };
Alexey Brodkin9de50582019-10-08 13:24:29 +030045
46 mmcclk_biu: mmcclk-biu {
47 compatible = "fixed-clock";
48 clock-frequency = <50000000>;
49 #clock-cells = <0>;
50 };
51
52 mmcclk_ciu: mmcclk-ciu {
53 compatible = "fixed-clock";
54 clock-frequency = <50000000>;
55 #clock-cells = <0>;
56 };
57
58 mmc: mmc0@f000b000 {
59 compatible = "snps,dw-mshc";
60 reg = <0xf000b000 0x400>;
61 bus-width = <4>;
62 fifo-depth = <128>;
63 clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
64 clock-names = "biu", "ciu";
65 max-frequency = <25000000>;
66 };
Alexey Brodkinc15be5b2018-01-24 21:37:14 +030067};