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git01.mediatek.com / filogic / uboot / 48704798d298009a0344d80e00329f0d9777c354 / . / arch / arm / include / asm / arch-exynos / dsim.h
blob: 86ff4da4d8e06cb728a3b3b4f29bb51d8ea76d92 [file] [log] [blame]
Donghwa Leed84f7832012-04-05 19:36:21 +0000[diff] [blame]1/*
2 * Copyright (C) 2012 Samsung Electronics
3 *
4 * Author: InKi Dae <inki.dae@samsung.com>
5 * Author: Donghwa Lee <dh09.lee@samsung.com>
6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Donghwa Leed84f7832012-04-05 19:36:21 +0000[diff] [blame]8 */
9
10#ifndef __ASM_ARM_ARCH_DSIM_H_
11#define __ASM_ARM_ARCH_DSIM_H_
12
13#ifndef __ASSEMBLY__
14
15struct exynos_mipi_dsim {
16 unsigned int status;
17 unsigned int swrst;
18 unsigned int clkctrl;
19 unsigned int timeout;
20 unsigned int config;
21 unsigned int escmode;
22 unsigned int mdresol;
23 unsigned int mvporch;
24 unsigned int mhporch;
25 unsigned int msync;
26 unsigned int sdresol;
27 unsigned int intsrc;
28 unsigned int intmsk;
29 unsigned int pkthdr;
30 unsigned int payload;
31 unsigned int rxfifo;
32 unsigned int fifothld;
33 unsigned int fifoctrl;
34 unsigned int memacchr;
35 unsigned int pllctrl;
36 unsigned int plltmr;
37 unsigned int phyacchr;
38 unsigned int phyacchr1;
39};
40
41#endif /* __ASSEMBLY__ */
42
43/*
44 * Bit Definitions
45 */
46/* DSIM_STATUS */
47#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
48#define DSIM_STOP_STATE_CLK (1 << 8)
49#define DSIM_TX_READY_HS_CLK (1 << 10)
50#define DSIM_PLL_STABLE (1 << 31)
51
52/* DSIM_SWRST */
53#define DSIM_FUNCRST (1 << 16)
54#define DSIM_SWRST (1 << 0)
55
56/* EXYNOS_DSIM_TIMEOUT */
57#define DSIM_LPDR_TOUT_SHIFT (0)
58#define DSIM_BTA_TOUT_SHIFT (16)
59
60/* EXYNOS_DSIM_CLKCTRL */
61#define DSIM_LANE_ESC_CLKEN_SHIFT (19)
62#define DSIM_BYTE_CLKEN_SHIFT (24)
63#define DSIM_BYTE_CLK_SRC_SHIFT (25)
64#define DSIM_PLL_BYPASS_SHIFT (27)
65#define DSIM_ESC_CLKEN_SHIFT (28)
66#define DSIM_TX_REQUEST_HSCLK_SHIFT (31)
67#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << \
68 DSIM_LANE_ESC_CLKEN_SHIFT)
69#define DSIM_BYTE_CLK_ENABLE (1 << DSIM_BYTE_CLKEN_SHIFT)
70#define DSIM_BYTE_CLK_DISABLE (0 << DSIM_BYTE_CLKEN_SHIFT)
71#define DSIM_PLL_BYPASS_EXTERNAL (1 << DSIM_PLL_BYPASS_SHIFT)
72#define DSIM_ESC_CLKEN_ENABLE (1 << DSIM_ESC_CLKEN_SHIFT)
73#define DSIM_ESC_CLKEN_DISABLE (0 << DSIM_ESC_CLKEN_SHIFT)
74
75/* EXYNOS_DSIM_CONFIG */
76#define DSIM_NUM_OF_DATALANE_SHIFT (5)
77#define DSIM_SUBPIX_SHIFT (8)
78#define DSIM_MAINPIX_SHIFT (12)
79#define DSIM_SUBVC_SHIFT (16)
80#define DSIM_MAINVC_SHIFT (18)
81#define DSIM_HSA_MODE_SHIFT (20)
82#define DSIM_HBP_MODE_SHIFT (21)
83#define DSIM_HFP_MODE_SHIFT (22)
84#define DSIM_HSE_MODE_SHIFT (23)
85#define DSIM_AUTO_MODE_SHIFT (24)
86#define DSIM_VIDEO_MODE_SHIFT (25)
87#define DSIM_BURST_MODE_SHIFT (26)
88#define DSIM_EOT_PACKET_SHIFT (28)
89#define DSIM_AUTO_FLUSH_SHIFT (29)
90#define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0)
91
92#define DSIM_NUM_OF_DATA_LANE(x) ((x) << DSIM_NUM_OF_DATALANE_SHIFT)
93
94/* EXYNOS_DSIM_ESCMODE */
95#define DSIM_TX_LPDT_SHIFT (6)
96#define DSIM_CMD_LPDT_SHIFT (7)
97#define DSIM_TX_LPDT_LP (1 << DSIM_TX_LPDT_SHIFT)
98#define DSIM_CMD_LPDT_LP (1 << DSIM_CMD_LPDT_SHIFT)
99#define DSIM_STOP_STATE_CNT_SHIFT (21)
100#define DSIM_FORCE_STOP_STATE_SHIFT (20)
101
102/* EXYNOS_DSIM_MDRESOL */
103#define DSIM_MAIN_STAND_BY (1 << 31)
104#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
105#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
106
107/* EXYNOS_DSIM_MVPORCH */
108#define DSIM_CMD_ALLOW_SHIFT (28)
109#define DSIM_STABLE_VFP_SHIFT (16)
110#define DSIM_MAIN_VBP_SHIFT (0)
111#define DSIM_CMD_ALLOW_MASK (0xf << DSIM_CMD_ALLOW_SHIFT)
112#define DSIM_STABLE_VFP_MASK (0x7ff << DSIM_STABLE_VFP_SHIFT)
113#define DSIM_MAIN_VBP_MASK (0x7ff << DSIM_MAIN_VBP_SHIFT)
114
115/* EXYNOS_DSIM_MHPORCH */
116#define DSIM_MAIN_HFP_SHIFT (16)
117#define DSIM_MAIN_HBP_SHIFT (0)
118#define DSIM_MAIN_HFP_MASK ((0xffff) << DSIM_MAIN_HFP_SHIFT)
119#define DSIM_MAIN_HBP_MASK ((0xffff) << DSIM_MAIN_HBP_SHIFT)
120
121/* EXYNOS_DSIM_MSYNC */
122#define DSIM_MAIN_VSA_SHIFT (22)
123#define DSIM_MAIN_HSA_SHIFT (0)
124#define DSIM_MAIN_VSA_MASK ((0x3ff) << DSIM_MAIN_VSA_SHIFT)
125#define DSIM_MAIN_HSA_MASK ((0xffff) << DSIM_MAIN_HSA_SHIFT)
126
127/* EXYNOS_DSIM_SDRESOL */
128#define DSIM_SUB_STANDY_SHIFT (31)
129#define DSIM_SUB_VRESOL_SHIFT (16)
130#define DSIM_SUB_HRESOL_SHIFT (0)
131#define DSIM_SUB_STANDY_MASK ((0x1) << DSIM_SUB_STANDY_SHIFT)
132#define DSIM_SUB_VRESOL_MASK ((0x7ff) << DSIM_SUB_VRESOL_SHIFT)
133#define DSIM_SUB_HRESOL_MASK ((0x7ff) << DSIM_SUB_HRESOL_SHIFT)
134
135/* EXYNOS_DSIM_INTSRC */
136#define INTSRC_FRAME_DONE (1 << 24)
137#define INTSRC_PLL_STABLE (1 << 31)
138#define INTSRC_SWRST_RELEASE (1 << 30)
139
140/* EXYNOS_DSIM_INTMSK */
141#define INTMSK_FRAME_DONE (1 << 24)
142
143/* EXYNOS_DSIM_FIFOCTRL */
144#define SFR_HEADER_EMPTY (1 << 22)
145
146/* EXYNOS_DSIM_PKTHDR */
147#define DSIM_PKTHDR_DI(x) (((x) & 0x3f) << 0)
148#define DSIM_PKTHDR_DAT0(x) ((x) << 8)
149#define DSIM_PKTHDR_DAT1(x) ((x) << 16)
150
151/* EXYNOS_DSIM_PHYACCHR */
152#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
153#define DSIM_AFC_CTL_SHIFT (5)
154#define DSIM_AFC_EN (1 << 14)
155
156/* EXYNOS_DSIM_PHYACCHR1 */
157#define DSIM_DPDN_SWAP_DATA_SHIFT (0)
158
159/* EXYNOS_DSIM_PLLCTRL */
160#define DSIM_SCALER_SHIFT (1)
161#define DSIM_MAIN_SHIFT (4)
162#define DSIM_PREDIV_SHIFT (13)
163#define DSIM_PRECTRL_SHIFT (20)
164#define DSIM_PLL_EN_SHIFT (23)
165#define DSIM_FREQ_BAND_SHIFT (24)
166#define DSIM_ZEROCTRL_SHIFT (28)
167
168#endif