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git01.mediatek.com / filogic / uboot / 48500f43f6a5fb2c25b4b75af02acda9711b0e06 / . / dts / upstream / src / arm64 / renesas / r9a09g057.dtsi
blob: 1ad5a1b6917fee3e11203a5a62350d8c824bc73a [file] [log] [blame]
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/V2H(P) SoC
4 *
5 * Copyright (C) 2024 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12 compatible = "renesas,r9a09g057";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 audio_extal_clk: audio-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 /* This value must be overridden by the board */
20 clock-frequency = <0>;
21 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu0: cpu@0 {
28 compatible = "arm,cortex-a55";
29 reg = <0>;
30 device_type = "cpu";
31 next-level-cache = <&L3_CA55>;
32 enable-method = "psci";
33 };
34
35 cpu1: cpu@100 {
36 compatible = "arm,cortex-a55";
37 reg = <0x100>;
38 device_type = "cpu";
39 next-level-cache = <&L3_CA55>;
40 enable-method = "psci";
41 };
42
43 cpu2: cpu@200 {
44 compatible = "arm,cortex-a55";
45 reg = <0x200>;
46 device_type = "cpu";
47 next-level-cache = <&L3_CA55>;
48 enable-method = "psci";
49 };
50
51 cpu3: cpu@300 {
52 compatible = "arm,cortex-a55";
53 reg = <0x300>;
54 device_type = "cpu";
55 next-level-cache = <&L3_CA55>;
56 enable-method = "psci";
57 };
58
59 L3_CA55: cache-controller-0 {
60 compatible = "cache";
61 cache-unified;
62 cache-size = <0x100000>;
63 cache-level = <3>;
64 };
65 };
66
67 psci {
68 compatible = "arm,psci-1.0", "arm,psci-0.2";
69 method = "smc";
70 };
71
72 qextal_clk: qextal-clk {
73 compatible = "fixed-clock";
74 #clock-cells = <0>;
75 /* This value must be overridden by the board */
76 clock-frequency = <0>;
77 };
78
79 rtxin_clk: rtxin-clk {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 /* This value must be overridden by the board */
83 clock-frequency = <0>;
84 };
85
86 soc: soc {
87 compatible = "simple-bus";
88 interrupt-parent = <&gic>;
89 #address-cells = <2>;
90 #size-cells = <2>;
91 ranges;
92
93 pinctrl: pinctrl@10410000 {
94 compatible = "renesas,r9a09g057-pinctrl";
95 reg = <0 0x10410000 0 0x10000>;
96 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>;
97 gpio-controller;
98 #gpio-cells = <2>;
99 gpio-ranges = <&pinctrl 0 0 96>;
100 #interrupt-cells = <2>;
101 interrupt-controller;
102 power-domains = <&cpg>;
103 resets = <&cpg 0xa5>, <&cpg 0xa6>;
104 };
105
106 cpg: clock-controller@10420000 {
107 compatible = "renesas,r9a09g057-cpg";
108 reg = <0 0x10420000 0 0x10000>;
109 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
110 clock-names = "audio_extal", "rtxin", "qextal";
111 #clock-cells = <2>;
112 #reset-cells = <1>;
113 #power-domain-cells = <0>;
114 };
115
116 sys: system-controller@10430000 {
117 compatible = "renesas,r9a09g057-sys";
118 reg = <0 0x10430000 0 0x10000>;
119 clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>;
120 resets = <&cpg 0x30>;
121 status = "disabled";
122 };
123
124 ostm0: timer@11800000 {
125 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
126 reg = <0x0 0x11800000 0x0 0x1000>;
127 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>;
128 clocks = <&cpg CPG_MOD 0x43>;
129 resets = <&cpg 0x6d>;
130 power-domains = <&cpg>;
131 status = "disabled";
132 };
133
134 ostm1: timer@11801000 {
135 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
136 reg = <0x0 0x11801000 0x0 0x1000>;
137 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>;
138 clocks = <&cpg CPG_MOD 0x44>;
139 resets = <&cpg 0x6e>;
140 power-domains = <&cpg>;
141 status = "disabled";
142 };
143
144 ostm2: timer@14000000 {
145 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
146 reg = <0x0 0x14000000 0x0 0x1000>;
147 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>;
148 clocks = <&cpg CPG_MOD 0x45>;
149 resets = <&cpg 0x6f>;
150 power-domains = <&cpg>;
151 status = "disabled";
152 };
153
154 ostm3: timer@14001000 {
155 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
156 reg = <0x0 0x14001000 0x0 0x1000>;
157 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>;
158 clocks = <&cpg CPG_MOD 0x46>;
159 resets = <&cpg 0x70>;
160 power-domains = <&cpg>;
161 status = "disabled";
162 };
163
164 ostm4: timer@12c00000 {
165 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
166 reg = <0x0 0x12c00000 0x0 0x1000>;
167 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
168 clocks = <&cpg CPG_MOD 0x47>;
169 resets = <&cpg 0x71>;
170 power-domains = <&cpg>;
171 status = "disabled";
172 };
173
174 ostm5: timer@12c01000 {
175 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
176 reg = <0x0 0x12c01000 0x0 0x1000>;
177 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
178 clocks = <&cpg CPG_MOD 0x48>;
179 resets = <&cpg 0x72>;
180 power-domains = <&cpg>;
181 status = "disabled";
182 };
183
184 ostm6: timer@12c02000 {
185 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
186 reg = <0x0 0x12c02000 0x0 0x1000>;
187 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
188 clocks = <&cpg CPG_MOD 0x49>;
189 resets = <&cpg 0x73>;
190 power-domains = <&cpg>;
191 status = "disabled";
192 };
193
194 ostm7: timer@12c03000 {
195 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
196 reg = <0x0 0x12c03000 0x0 0x1000>;
197 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
198 clocks = <&cpg CPG_MOD 0x4a>;
199 resets = <&cpg 0x74>;
200 power-domains = <&cpg>;
201 status = "disabled";
202 };
203
204 wdt0: watchdog@11c00400 {
205 compatible = "renesas,r9a09g057-wdt";
206 reg = <0 0x11c00400 0 0x400>;
207 clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
208 clock-names = "pclk", "oscclk";
209 resets = <&cpg 0x75>;
210 power-domains = <&cpg>;
211 status = "disabled";
212 };
213
214 wdt1: watchdog@14400000 {
215 compatible = "renesas,r9a09g057-wdt";
216 reg = <0 0x14400000 0 0x400>;
217 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
218 clock-names = "pclk", "oscclk";
219 resets = <&cpg 0x76>;
220 power-domains = <&cpg>;
221 status = "disabled";
222 };
223
224 wdt2: watchdog@13000000 {
225 compatible = "renesas,r9a09g057-wdt";
226 reg = <0 0x13000000 0 0x400>;
227 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
228 clock-names = "pclk", "oscclk";
229 resets = <&cpg 0x77>;
230 power-domains = <&cpg>;
231 status = "disabled";
232 };
233
234 wdt3: watchdog@13000400 {
235 compatible = "renesas,r9a09g057-wdt";
236 reg = <0 0x13000400 0 0x400>;
237 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
238 clock-names = "pclk", "oscclk";
239 resets = <&cpg 0x78>;
240 power-domains = <&cpg>;
241 status = "disabled";
242 };
243
244 scif: serial@11c01400 {
245 compatible = "renesas,scif-r9a09g057";
246 reg = <0 0x11c01400 0 0x400>;
247 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
255 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
256 interrupt-names = "eri", "rxi", "txi", "bri", "dri",
257 "tei", "tei-dri", "rxi-edge", "txi-edge";
258 clocks = <&cpg CPG_MOD 0x8f>;
259 clock-names = "fck";
260 power-domains = <&cpg>;
261 resets = <&cpg 0x95>;
262 status = "disabled";
263 };
264
265 i2c0: i2c@14400400 {
266 compatible = "renesas,riic-r9a09g057";
267 reg = <0 0x14400400 0 0x400>;
268 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>,
270 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>,
271 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "tei", "ri", "ti", "spi", "sti",
277 "naki", "ali", "tmoi";
278 clocks = <&cpg CPG_MOD 0x94>;
279 resets = <&cpg 0x98>;
280 power-domains = <&cpg>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 status = "disabled";
284 };
285
286 i2c1: i2c@14400800 {
287 compatible = "renesas,riic-r9a09g057";
288 reg = <0 0x14400800 0 0x400>;
289 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>,
291 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>,
292 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
297 interrupt-names = "tei", "ri", "ti", "spi", "sti",
298 "naki", "ali", "tmoi";
299 clocks = <&cpg CPG_MOD 0x95>;
300 resets = <&cpg 0x99>;
301 power-domains = <&cpg>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304 status = "disabled";
305 };
306
307 i2c2: i2c@14400c00 {
308 compatible = "renesas,riic-r9a09g057";
309 reg = <0 0x14400c00 0 0x400>;
310 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>,
312 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>,
313 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
318 interrupt-names = "tei", "ri", "ti", "spi", "sti",
319 "naki", "ali", "tmoi";
320 clocks = <&cpg CPG_MOD 0x96>;
321 resets = <&cpg 0x9a>;
322 power-domains = <&cpg>;
323 #address-cells = <1>;
324 #size-cells = <0>;
325 status = "disabled";
326 };
327
328 i2c3: i2c@14401000 {
329 compatible = "renesas,riic-r9a09g057";
330 reg = <0 0x14401000 0 0x400>;
331 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>,
333 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>,
334 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
339 interrupt-names = "tei", "ri", "ti", "spi", "sti",
340 "naki", "ali", "tmoi";
341 clocks = <&cpg CPG_MOD 0x97>;
342 resets = <&cpg 0x9b>;
343 power-domains = <&cpg>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 status = "disabled";
347 };
348
349 i2c4: i2c@14401400 {
350 compatible = "renesas,riic-r9a09g057";
351 reg = <0 0x14401400 0 0x400>;
352 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>,
354 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>,
355 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-names = "tei", "ri", "ti", "spi", "sti",
361 "naki", "ali", "tmoi";
362 clocks = <&cpg CPG_MOD 0x98>;
363 resets = <&cpg 0x9c>;
364 power-domains = <&cpg>;
365 #address-cells = <1>;
366 #size-cells = <0>;
367 status = "disabled";
368 };
369
370 i2c5: i2c@14401800 {
371 compatible = "renesas,riic-r9a09g057";
372 reg = <0 0x14401800 0 0x400>;
373 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>,
375 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>,
376 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
381 interrupt-names = "tei", "ri", "ti", "spi", "sti",
382 "naki", "ali", "tmoi";
383 clocks = <&cpg CPG_MOD 0x99>;
384 resets = <&cpg 0x9d>;
385 power-domains = <&cpg>;
386 #address-cells = <1>;
387 #size-cells = <0>;
388 status = "disabled";
389 };
390
391 i2c6: i2c@14401c00 {
392 compatible = "renesas,riic-r9a09g057";
393 reg = <0 0x14401c00 0 0x400>;
394 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>,
396 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>,
397 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "tei", "ri", "ti", "spi", "sti",
403 "naki", "ali", "tmoi";
404 clocks = <&cpg CPG_MOD 0x9a>;
405 resets = <&cpg 0x9e>;
406 power-domains = <&cpg>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409 status = "disabled";
410 };
411
412 i2c7: i2c@14402000 {
413 compatible = "renesas,riic-r9a09g057";
414 reg = <0 0x14402000 0 0x400>;
415 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>,
417 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>,
418 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
423 interrupt-names = "tei", "ri", "ti", "spi", "sti",
424 "naki", "ali", "tmoi";
425 clocks = <&cpg CPG_MOD 0x9b>;
426 resets = <&cpg 0x9f>;
427 power-domains = <&cpg>;
428 #address-cells = <1>;
429 #size-cells = <0>;
430 status = "disabled";
431 };
432
433 i2c8: i2c@11c01000 {
434 compatible = "renesas,riic-r9a09g057";
435 reg = <0 0x11c01000 0 0x400>;
436 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>,
438 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>,
439 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
444 interrupt-names = "tei", "ri", "ti", "spi", "sti",
445 "naki", "ali", "tmoi";
446 clocks = <&cpg CPG_MOD 0x93>;
447 resets = <&cpg 0xa0>;
448 power-domains = <&cpg>;
449 #address-cells = <1>;
450 #size-cells = <0>;
451 status = "disabled";
452 };
453
454 gic: interrupt-controller@14900000 {
455 compatible = "arm,gic-v3";
456 reg = <0x0 0x14900000 0 0x20000>,
457 <0x0 0x14940000 0 0x80000>;
458 #interrupt-cells = <3>;
459 #address-cells = <0>;
460 interrupt-controller;
461 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
462 };
463
464 sdhi0: mmc@15c00000 {
465 compatible = "renesas,sdhi-r9a09g057";
466 reg = <0x0 0x15c00000 0 0x10000>;
467 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
470 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
471 clock-names = "core", "clkh", "cd", "aclk";
472 resets = <&cpg 0xa7>;
473 power-domains = <&cpg>;
474 status = "disabled";
475 };
476
477 sdhi1: mmc@15c10000 {
478 compatible = "renesas,sdhi-r9a09g057";
479 reg = <0x0 0x15c10000 0 0x10000>;
480 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>,
483 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>;
484 clock-names = "core", "clkh", "cd", "aclk";
485 resets = <&cpg 0xa8>;
486 power-domains = <&cpg>;
487 status = "disabled";
488 };
489
490 sdhi2: mmc@15c20000 {
491 compatible = "renesas,sdhi-r9a09g057";
492 reg = <0x0 0x15c20000 0 0x10000>;
493 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>,
496 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>;
497 clock-names = "core", "clkh", "cd", "aclk";
498 resets = <&cpg 0xa9>;
499 power-domains = <&cpg>;
500 status = "disabled";
501 };
502 };
503
504 timer {
505 compatible = "arm,armv8-timer";
506 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
507 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
508 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
509 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
510 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
511 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
512 };
513};