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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkedc48b62002-09-08 17:56:50 +00002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkedc48b62002-09-08 17:56:50 +00005 */
6
7/* for now: just dummy functions to satisfy the linker */
8
wdenkf8062712005-01-09 23:16:25 +00009#include <common.h>
Simon Glass63334482019-11-14 12:57:39 -070010#include <cpu_func.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Thierry Redingc97d9742014-12-09 22:25:22 -070012#include <malloc.h>
Simon Glass274e0b02020-05-10 11:39:56 -060013#include <asm/cache.h>
wdenkf8062712005-01-09 23:16:25 +000014
Ovidiu Panait68b371a2020-03-29 20:57:39 +030015DECLARE_GLOBAL_DATA_PTR;
16
Wu, Josh22190262015-07-27 11:40:17 +080017/*
18 * Flush range from all levels of d-cache/unified-cache.
19 * Affects the range [start, start + size - 1].
20 */
Jeroen Hofsteed7460772014-06-23 22:07:04 +020021__weak void flush_cache(unsigned long start, unsigned long size)
wdenkedc48b62002-09-08 17:56:50 +000022{
Wu, Josh22190262015-07-27 11:40:17 +080023 flush_dcache_range(start, start + size);
wdenkedc48b62002-09-08 17:56:50 +000024}
Aneesh V3bda3772011-06-16 23:30:50 +000025
26/*
27 * Default implementation:
28 * do a range flush for the entire range
29 */
Jeroen Hofsteed7460772014-06-23 22:07:04 +020030__weak void flush_dcache_all(void)
Aneesh V3bda3772011-06-16 23:30:50 +000031{
32 flush_cache(0, ~0);
33}
Aneesh Vfffbb972011-08-16 04:33:05 +000034
35/*
36 * Default implementation of enable_caches()
37 * Real implementation should be in platform code
38 */
Jeroen Hofsteed7460772014-06-23 22:07:04 +020039__weak void enable_caches(void)
Aneesh Vfffbb972011-08-16 04:33:05 +000040{
41 puts("WARNING: Caches not enabled\n");
42}
Thierry Redingc97d9742014-12-09 22:25:22 -070043
Wu, Joshaaa35452015-07-27 11:40:16 +080044__weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
45{
46 /* An empty stub, real implementation should be in platform code */
47}
48__weak void flush_dcache_range(unsigned long start, unsigned long stop)
49{
50 /* An empty stub, real implementation should be in platform code */
51}
52
Simon Glass85406582016-06-19 19:43:01 -060053int check_cache_range(unsigned long start, unsigned long stop)
54{
55 int ok = 1;
56
57 if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
58 ok = 0;
59
60 if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
61 ok = 0;
62
63 if (!ok) {
Simon Glass143997a2016-06-19 19:43:05 -060064 warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
65 start, stop);
Simon Glass85406582016-06-19 19:43:01 -060066 }
67
68 return ok;
69}
70
Thierry Redingc97d9742014-12-09 22:25:22 -070071#ifdef CONFIG_SYS_NONCACHED_MEMORY
72/*
73 * Reserve one MMU section worth of address space below the malloc() area that
74 * will be mapped uncached.
75 */
76static unsigned long noncached_start;
77static unsigned long noncached_end;
78static unsigned long noncached_next;
79
Patrice Chotarde2eb7212020-04-28 11:38:03 +020080void noncached_set_region(void)
81{
82#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
83 mmu_set_region_dcache_behaviour(noncached_start,
84 noncached_end - noncached_start,
85 DCACHE_OFF);
86#endif
87}
88
Ovidiu Panait1c45ed92020-11-28 10:43:13 +020089int noncached_init(void)
Thierry Redingc97d9742014-12-09 22:25:22 -070090{
91 phys_addr_t start, end;
92 size_t size;
93
Stephen Warren9b496432019-08-27 11:54:31 -060094 /* If this calculation changes, update board_f.c:reserve_noncached() */
Thierry Redingc97d9742014-12-09 22:25:22 -070095 end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
96 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
97 start = end - size;
98
99 debug("mapping memory %pa-%pa non-cached\n", &start, &end);
100
101 noncached_start = start;
102 noncached_end = end;
103 noncached_next = start;
104
Patrice Chotarde2eb7212020-04-28 11:38:03 +0200105 noncached_set_region();
Ovidiu Panait1c45ed92020-11-28 10:43:13 +0200106
107 return 0;
Thierry Redingc97d9742014-12-09 22:25:22 -0700108}
109
110phys_addr_t noncached_alloc(size_t size, size_t align)
111{
112 phys_addr_t next = ALIGN(noncached_next, align);
113
114 if (next >= noncached_end || (noncached_end - next) < size)
115 return 0;
116
117 debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
118 noncached_next = next + size;
119
120 return next;
121}
122#endif /* CONFIG_SYS_NONCACHED_MEMORY */
Albert ARIBAUDa3823222015-10-23 18:06:40 +0200123
Tom Rini1c640a62017-03-18 09:01:44 -0400124#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
Albert ARIBAUDa3823222015-10-23 18:06:40 +0200125void invalidate_l2_cache(void)
126{
127 unsigned int val = 0;
128
129 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
130 : : "r" (val) : "cc");
131 isb();
132}
133#endif
Ovidiu Panait68b371a2020-03-29 20:57:39 +0300134
Ovidiu Panait2a2941b2020-03-29 20:57:41 +0300135int arch_reserve_mmu(void)
Ovidiu Panait68b371a2020-03-29 20:57:39 +0300136{
Ovidiu Panait2b618472020-03-29 20:57:40 +0300137 return arm_reserve_mmu();
138}
139
140__weak int arm_reserve_mmu(void)
141{
Ovidiu Panait68b371a2020-03-29 20:57:39 +0300142#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
143 /* reserve TLB table */
144 gd->arch.tlb_size = PGTABLE_SIZE;
145 gd->relocaddr -= gd->arch.tlb_size;
146
147 /* round down to next 64 kB limit */
148 gd->relocaddr &= ~(0x10000 - 1);
149
150 gd->arch.tlb_addr = gd->relocaddr;
151 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
152 gd->arch.tlb_addr + gd->arch.tlb_size);
153
154#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
155 /*
156 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
157 * with location within secure ram.
158 */
159 gd->arch.tlb_allocated = gd->arch.tlb_addr;
160#endif
161#endif
162
163 return 0;
164}