Dario Binacchi | 96d04d7 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 1 | &l4_wkup { /* 0x44c00000 */ |
| 2 | compatible = "ti,am33xx-l4-wkup", "simple-bus"; |
| 3 | reg = <0x44c00000 0x800>, |
| 4 | <0x44c00800 0x800>, |
| 5 | <0x44c01000 0x400>, |
| 6 | <0x44c01400 0x400>; |
| 7 | reg-names = "ap", "la", "ia0", "ia1"; |
| 8 | #address-cells = <1>; |
| 9 | #size-cells = <1>; |
| 10 | ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ |
| 11 | <0x00100000 0x44d00000 0x100000>, /* segment 1 */ |
| 12 | <0x00200000 0x44e00000 0x100000>; /* segment 2 */ |
| 13 | |
| 14 | segment@0 { /* 0x44c00000 */ |
| 15 | compatible = "simple-bus"; |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; |
| 18 | ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ |
| 19 | <0x00000800 0x00000800 0x000800>, /* ap 1 */ |
| 20 | <0x00001000 0x00001000 0x000400>, /* ap 2 */ |
| 21 | <0x00001400 0x00001400 0x000400>; /* ap 3 */ |
| 22 | }; |
| 23 | |
| 24 | segment@100000 { /* 0x44d00000 */ |
| 25 | compatible = "simple-bus"; |
| 26 | #address-cells = <1>; |
| 27 | #size-cells = <1>; |
| 28 | ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ |
| 29 | <0x00004000 0x00104000 0x001000>, /* ap 5 */ |
| 30 | <0x00080000 0x00180000 0x002000>, /* ap 6 */ |
| 31 | <0x00082000 0x00182000 0x001000>; /* ap 7 */ |
| 32 | |
| 33 | target-module@0 { /* 0x44d00000, ap 4 28.0 */ |
| 34 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 35 | reg = <0x0 0x4>; |
| 36 | reg-names = "rev"; |
| 37 | #address-cells = <1>; |
| 38 | #size-cells = <1>; |
| 39 | ranges = <0x0 0x0 0x4000>; |
| 40 | status = "disabled"; |
| 41 | }; |
| 42 | |
| 43 | target-module@80000 { /* 0x44d80000, ap 6 10.0 */ |
| 44 | compatible = "ti,sysc"; |
| 45 | status = "disabled"; |
| 46 | #address-cells = <1>; |
| 47 | #size-cells = <1>; |
| 48 | ranges = <0x0 0x80000 0x2000>; |
| 49 | }; |
| 50 | }; |
| 51 | |
| 52 | segment@200000 { /* 0x44e00000 */ |
| 53 | compatible = "simple-bus"; |
| 54 | #address-cells = <1>; |
| 55 | #size-cells = <1>; |
| 56 | ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ |
| 57 | <0x00002000 0x00202000 0x001000>, /* ap 9 */ |
| 58 | <0x00003000 0x00203000 0x001000>, /* ap 10 */ |
| 59 | <0x00004000 0x00204000 0x001000>, /* ap 11 */ |
| 60 | <0x00005000 0x00205000 0x001000>, /* ap 12 */ |
| 61 | <0x00006000 0x00206000 0x001000>, /* ap 13 */ |
| 62 | <0x00007000 0x00207000 0x001000>, /* ap 14 */ |
| 63 | <0x00008000 0x00208000 0x001000>, /* ap 15 */ |
| 64 | <0x00009000 0x00209000 0x001000>, /* ap 16 */ |
| 65 | <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ |
| 66 | <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ |
| 67 | <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ |
| 68 | <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ |
| 69 | <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ |
| 70 | <0x00010000 0x00210000 0x010000>, /* ap 22 */ |
| 71 | <0x00020000 0x00220000 0x010000>, /* ap 23 */ |
| 72 | <0x00030000 0x00230000 0x001000>, /* ap 24 */ |
| 73 | <0x00031000 0x00231000 0x001000>, /* ap 25 */ |
| 74 | <0x00032000 0x00232000 0x001000>, /* ap 26 */ |
| 75 | <0x00033000 0x00233000 0x001000>, /* ap 27 */ |
| 76 | <0x00034000 0x00234000 0x001000>, /* ap 28 */ |
| 77 | <0x00035000 0x00235000 0x001000>, /* ap 29 */ |
| 78 | <0x00036000 0x00236000 0x001000>, /* ap 30 */ |
| 79 | <0x00037000 0x00237000 0x001000>, /* ap 31 */ |
| 80 | <0x00038000 0x00238000 0x001000>, /* ap 32 */ |
| 81 | <0x00039000 0x00239000 0x001000>, /* ap 33 */ |
| 82 | <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ |
| 83 | <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ |
| 84 | <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ |
| 85 | <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ |
| 86 | <0x00040000 0x00240000 0x040000>, /* ap 38 */ |
| 87 | <0x00080000 0x00280000 0x001000>; /* ap 39 */ |
| 88 | |
| 89 | target-module@0 { /* 0x44e00000, ap 8 58.0 */ |
| 90 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 91 | reg = <0 0x4>; |
| 92 | reg-names = "rev"; |
| 93 | #address-cells = <1>; |
| 94 | #size-cells = <1>; |
| 95 | ranges = <0x0 0x0 0x2000>; |
| 96 | |
| 97 | prcm: prcm@0 { |
| 98 | compatible = "ti,am3-prcm", "simple-bus"; |
| 99 | reg = <0 0x2000>; |
| 100 | #address-cells = <1>; |
| 101 | #size-cells = <1>; |
| 102 | ranges = <0 0 0x2000>; |
| 103 | |
| 104 | prcm_clocks: clocks { |
| 105 | #address-cells = <1>; |
| 106 | #size-cells = <0>; |
| 107 | }; |
| 108 | |
| 109 | prcm_clockdomains: clockdomains { |
| 110 | }; |
| 111 | }; |
| 112 | }; |
| 113 | |
| 114 | target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ |
| 115 | compatible = "ti,sysc"; |
| 116 | status = "disabled"; |
| 117 | #address-cells = <1>; |
| 118 | #size-cells = <1>; |
| 119 | ranges = <0x0 0x3000 0x1000>; |
| 120 | }; |
| 121 | |
| 122 | target-module@5000 { /* 0x44e05000, ap 12 30.0 */ |
| 123 | compatible = "ti,sysc"; |
| 124 | status = "disabled"; |
| 125 | #address-cells = <1>; |
| 126 | #size-cells = <1>; |
| 127 | ranges = <0x0 0x5000 0x1000>; |
| 128 | }; |
| 129 | |
| 130 | gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ |
| 131 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 132 | reg = <0x7000 0x4>, |
| 133 | <0x7010 0x4>, |
| 134 | <0x7114 0x4>; |
| 135 | reg-names = "rev", "sysc", "syss"; |
| 136 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| 137 | SYSC_OMAP2_SOFTRESET | |
| 138 | SYSC_OMAP2_AUTOIDLE)>; |
| 139 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 140 | <SYSC_IDLE_NO>, |
| 141 | <SYSC_IDLE_SMART>, |
| 142 | <SYSC_IDLE_SMART_WKUP>; |
| 143 | ti,syss-mask = <1>; |
| 144 | /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ |
| 145 | clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, |
| 146 | <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; |
| 147 | clock-names = "fck", "dbclk"; |
| 148 | #address-cells = <1>; |
| 149 | #size-cells = <1>; |
| 150 | ranges = <0x0 0x7000 0x1000>; |
| 151 | }; |
| 152 | |
| 153 | target-module@9000 { /* 0x44e09000, ap 16 04.0 */ |
| 154 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 155 | reg = <0x9050 0x4>, |
| 156 | <0x9054 0x4>, |
| 157 | <0x9058 0x4>; |
| 158 | reg-names = "rev", "sysc", "syss"; |
| 159 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| 160 | SYSC_OMAP2_SOFTRESET | |
| 161 | SYSC_OMAP2_AUTOIDLE)>; |
| 162 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 163 | <SYSC_IDLE_NO>, |
| 164 | <SYSC_IDLE_SMART>, |
| 165 | <SYSC_IDLE_SMART_WKUP>; |
| 166 | /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ |
| 167 | clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; |
| 168 | clock-names = "fck"; |
| 169 | #address-cells = <1>; |
| 170 | #size-cells = <1>; |
| 171 | ranges = <0x0 0x9000 0x1000>; |
| 172 | |
| 173 | uart0: serial@0 { |
| 174 | compatible = "ti,am3352-uart", "ti,omap3-uart"; |
| 175 | clock-frequency = <48000000>; |
| 176 | reg = <0x0 0x1000>; |
| 177 | interrupts = <72>; |
| 178 | status = "disabled"; |
| 179 | dmas = <&edma 26 0>, <&edma 27 0>; |
| 180 | dma-names = "tx", "rx"; |
| 181 | }; |
| 182 | }; |
| 183 | |
| 184 | target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ |
| 185 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 186 | reg = <0xb000 0x8>, |
| 187 | <0xb010 0x8>, |
| 188 | <0xb090 0x8>; |
| 189 | reg-names = "rev", "sysc", "syss"; |
| 190 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| 191 | SYSC_OMAP2_ENAWAKEUP | |
| 192 | SYSC_OMAP2_SOFTRESET | |
| 193 | SYSC_OMAP2_AUTOIDLE)>; |
| 194 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 195 | <SYSC_IDLE_NO>, |
| 196 | <SYSC_IDLE_SMART>, |
| 197 | <SYSC_IDLE_SMART_WKUP>; |
| 198 | ti,syss-mask = <1>; |
| 199 | /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ |
| 200 | clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; |
| 201 | clock-names = "fck"; |
| 202 | #address-cells = <1>; |
| 203 | #size-cells = <1>; |
| 204 | ranges = <0x0 0xb000 0x1000>; |
| 205 | }; |
| 206 | |
| 207 | target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ |
| 208 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 209 | reg = <0xd000 0x4>, |
| 210 | <0xd010 0x4>; |
| 211 | reg-names = "rev", "sysc"; |
| 212 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 213 | <SYSC_IDLE_NO>, |
| 214 | <SYSC_IDLE_SMART>, |
| 215 | <SYSC_IDLE_SMART_WKUP>; |
| 216 | /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ |
| 217 | clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; |
| 218 | clock-names = "fck"; |
| 219 | #address-cells = <1>; |
| 220 | #size-cells = <1>; |
| 221 | ranges = <0x00000000 0x0000d000 0x00001000>, |
| 222 | <0x00001000 0x0000e000 0x00001000>; |
| 223 | |
| 224 | tscadc: tscadc@0 { |
| 225 | compatible = "ti,am3359-tscadc"; |
| 226 | reg = <0x0 0x1000>; |
| 227 | interrupts = <16>; |
| 228 | status = "disabled"; |
| 229 | dmas = <&edma 53 0>, <&edma 57 0>; |
| 230 | dma-names = "fifo0", "fifo1"; |
| 231 | |
| 232 | tsc { |
| 233 | compatible = "ti,am3359-tsc"; |
| 234 | }; |
| 235 | am335x_adc: adc { |
| 236 | #io-channel-cells = <1>; |
| 237 | compatible = "ti,am3359-adc"; |
| 238 | }; |
| 239 | }; |
| 240 | |
| 241 | }; |
| 242 | |
| 243 | target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ |
| 244 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 245 | reg = <0x10000 0x4>; |
| 246 | reg-names = "rev"; |
| 247 | #address-cells = <1>; |
| 248 | #size-cells = <1>; |
| 249 | ranges = <0x00000000 0x00010000 0x00010000>, |
| 250 | <0x00010000 0x00020000 0x00010000>; |
| 251 | |
| 252 | scm: scm@0 { |
| 253 | compatible = "ti,am3-scm", "simple-bus"; |
| 254 | reg = <0x0 0x2000>; |
| 255 | #address-cells = <1>; |
| 256 | #size-cells = <1>; |
| 257 | #pinctrl-cells = <1>; |
| 258 | ranges = <0 0 0x2000>; |
| 259 | |
| 260 | am33xx_pinmux: pinmux@800 { |
| 261 | compatible = "pinctrl-single"; |
| 262 | reg = <0x800 0x238>; |
| 263 | #pinctrl-cells = <2>; |
| 264 | pinctrl-single,register-width = <32>; |
| 265 | pinctrl-single,function-mask = <0x7f>; |
| 266 | }; |
| 267 | |
| 268 | scm_conf: scm_conf@0 { |
| 269 | compatible = "syscon", "simple-bus"; |
| 270 | reg = <0x0 0x800>; |
| 271 | #address-cells = <1>; |
| 272 | #size-cells = <1>; |
| 273 | ranges = <0 0 0x800>; |
| 274 | |
| 275 | phy_gmii_sel: phy-gmii-sel { |
| 276 | compatible = "ti,am3352-phy-gmii-sel"; |
| 277 | reg = <0x650 0x4>; |
| 278 | #phy-cells = <2>; |
| 279 | }; |
| 280 | |
| 281 | scm_clocks: clocks { |
| 282 | #address-cells = <1>; |
| 283 | #size-cells = <0>; |
| 284 | }; |
| 285 | }; |
| 286 | |
| 287 | wkup_m3_ipc: wkup_m3_ipc@1324 { |
| 288 | compatible = "ti,am3352-wkup-m3-ipc"; |
| 289 | reg = <0x1324 0x24>; |
| 290 | interrupts = <78>; |
| 291 | ti,rproc = <&wkup_m3>; |
| 292 | mboxes = <&mailbox &mbox_wkupm3>; |
| 293 | }; |
| 294 | |
| 295 | edma_xbar: dma-router@f90 { |
| 296 | compatible = "ti,am335x-edma-crossbar"; |
| 297 | reg = <0xf90 0x40>; |
| 298 | #dma-cells = <3>; |
| 299 | dma-requests = <32>; |
| 300 | dma-masters = <&edma>; |
| 301 | }; |
| 302 | |
| 303 | scm_clockdomains: clockdomains { |
| 304 | }; |
| 305 | }; |
| 306 | }; |
| 307 | |
| 308 | timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */ |
| 309 | compatible = "ti,sysc-omap2-timer", "ti,sysc"; |
| 310 | reg = <0x31000 0x4>, |
| 311 | <0x31010 0x4>, |
| 312 | <0x31014 0x4>; |
| 313 | reg-names = "rev", "sysc", "syss"; |
| 314 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| 315 | SYSC_OMAP2_SOFTRESET | |
| 316 | SYSC_OMAP2_AUTOIDLE)>; |
| 317 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 318 | <SYSC_IDLE_NO>, |
| 319 | <SYSC_IDLE_SMART>; |
| 320 | ti,syss-mask = <1>; |
| 321 | /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ |
| 322 | clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; |
| 323 | clock-names = "fck"; |
| 324 | #address-cells = <1>; |
| 325 | #size-cells = <1>; |
| 326 | ranges = <0x0 0x31000 0x1000>; |
| 327 | |
| 328 | timer1: timer@0 { |
| 329 | compatible = "ti,am335x-timer-1ms"; |
| 330 | reg = <0x0 0x400>; |
| 331 | interrupts = <67>; |
| 332 | ti,timer-alwon; |
| 333 | clocks = <&timer1_fck>; |
| 334 | clock-names = "fck"; |
| 335 | }; |
| 336 | }; |
| 337 | |
| 338 | target-module@33000 { /* 0x44e33000, ap 27 18.0 */ |
| 339 | compatible = "ti,sysc"; |
| 340 | status = "disabled"; |
| 341 | #address-cells = <1>; |
| 342 | #size-cells = <1>; |
| 343 | ranges = <0x0 0x33000 0x1000>; |
| 344 | }; |
| 345 | |
| 346 | target-module@35000 { /* 0x44e35000, ap 29 50.0 */ |
| 347 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 348 | reg = <0x35000 0x4>, |
| 349 | <0x35010 0x4>, |
| 350 | <0x35014 0x4>; |
| 351 | reg-names = "rev", "sysc", "syss"; |
| 352 | ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | |
| 353 | SYSC_OMAP2_SOFTRESET)>; |
| 354 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 355 | <SYSC_IDLE_NO>, |
| 356 | <SYSC_IDLE_SMART>, |
| 357 | <SYSC_IDLE_SMART_WKUP>; |
| 358 | ti,syss-mask = <1>; |
| 359 | /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ |
| 360 | clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; |
| 361 | clock-names = "fck"; |
| 362 | #address-cells = <1>; |
| 363 | #size-cells = <1>; |
| 364 | ranges = <0x0 0x35000 0x1000>; |
| 365 | }; |
| 366 | |
| 367 | target-module@37000 { /* 0x44e37000, ap 31 08.0 */ |
| 368 | compatible = "ti,sysc"; |
| 369 | status = "disabled"; |
| 370 | #address-cells = <1>; |
| 371 | #size-cells = <1>; |
| 372 | ranges = <0x0 0x37000 0x1000>; |
| 373 | }; |
| 374 | |
| 375 | target-module@39000 { /* 0x44e39000, ap 33 02.0 */ |
| 376 | compatible = "ti,sysc"; |
| 377 | status = "disabled"; |
| 378 | #address-cells = <1>; |
| 379 | #size-cells = <1>; |
| 380 | ranges = <0x0 0x39000 0x1000>; |
| 381 | }; |
| 382 | |
| 383 | target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ |
| 384 | compatible = "ti,sysc-omap4-simple", "ti,sysc"; |
| 385 | reg = <0x3e074 0x4>, |
| 386 | <0x3e078 0x4>; |
| 387 | reg-names = "rev", "sysc"; |
| 388 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 389 | <SYSC_IDLE_NO>, |
| 390 | <SYSC_IDLE_SMART>, |
| 391 | <SYSC_IDLE_SMART_WKUP>; |
| 392 | /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ |
| 393 | clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; |
| 394 | clock-names = "fck"; |
| 395 | #address-cells = <1>; |
| 396 | #size-cells = <1>; |
| 397 | ranges = <0x0 0x3e000 0x1000>; |
| 398 | |
| 399 | rtc: rtc@0 { |
| 400 | compatible = "ti,am3352-rtc", "ti,da830-rtc"; |
| 401 | reg = <0x0 0x1000>; |
| 402 | interrupts = <75 76>; |
| 403 | }; |
| 404 | }; |
| 405 | |
| 406 | target-module@40000 { /* 0x44e40000, ap 38 68.0 */ |
| 407 | compatible = "ti,sysc"; |
| 408 | status = "disabled"; |
| 409 | #address-cells = <1>; |
| 410 | #size-cells = <1>; |
| 411 | ranges = <0x0 0x40000 0x40000>; |
| 412 | }; |
| 413 | }; |
| 414 | }; |
| 415 | |
| 416 | &l4_fw { /* 0x47c00000 */ |
| 417 | compatible = "ti,am33xx-l4-fw", "simple-bus"; |
| 418 | reg = <0x47c00000 0x800>, |
| 419 | <0x47c00800 0x800>, |
| 420 | <0x47c01000 0x400>; |
| 421 | reg-names = "ap", "la", "ia0"; |
| 422 | #address-cells = <1>; |
| 423 | #size-cells = <1>; |
| 424 | ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ |
| 425 | |
| 426 | segment@0 { /* 0x47c00000 */ |
| 427 | compatible = "simple-bus"; |
| 428 | #address-cells = <1>; |
| 429 | #size-cells = <1>; |
| 430 | ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ |
| 431 | <0x00000800 0x00000800 0x000800>, /* ap 1 */ |
| 432 | <0x00001000 0x00001000 0x000400>, /* ap 2 */ |
| 433 | <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ |
| 434 | <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ |
| 435 | <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ |
| 436 | <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ |
| 437 | <0x00010000 0x00010000 0x001000>, /* ap 7 */ |
| 438 | <0x00011000 0x00011000 0x001000>, /* ap 8 */ |
| 439 | <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ |
| 440 | <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ |
| 441 | <0x00024000 0x00024000 0x001000>, /* ap 11 */ |
| 442 | <0x00025000 0x00025000 0x001000>, /* ap 12 */ |
| 443 | <0x00026000 0x00026000 0x001000>, /* ap 13 */ |
| 444 | <0x00027000 0x00027000 0x001000>, /* ap 14 */ |
| 445 | <0x00030000 0x00030000 0x001000>, /* ap 15 */ |
| 446 | <0x00031000 0x00031000 0x001000>, /* ap 16 */ |
| 447 | <0x00038000 0x00038000 0x001000>, /* ap 17 */ |
| 448 | <0x00039000 0x00039000 0x001000>, /* ap 18 */ |
| 449 | <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ |
| 450 | <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ |
| 451 | <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ |
| 452 | <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ |
| 453 | <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ |
| 454 | <0x00040000 0x00040000 0x001000>, /* ap 24 */ |
| 455 | <0x00046000 0x00046000 0x001000>, /* ap 25 */ |
| 456 | <0x00047000 0x00047000 0x001000>, /* ap 26 */ |
| 457 | <0x00044000 0x00044000 0x001000>, /* ap 27 */ |
| 458 | <0x00045000 0x00045000 0x001000>, /* ap 28 */ |
| 459 | <0x00028000 0x00028000 0x001000>, /* ap 29 */ |
| 460 | <0x00029000 0x00029000 0x001000>, /* ap 30 */ |
| 461 | <0x00032000 0x00032000 0x001000>, /* ap 31 */ |
| 462 | <0x00033000 0x00033000 0x001000>, /* ap 32 */ |
| 463 | <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ |
| 464 | <0x00041000 0x00041000 0x001000>, /* ap 34 */ |
| 465 | <0x00042000 0x00042000 0x001000>, /* ap 35 */ |
| 466 | <0x00043000 0x00043000 0x001000>, /* ap 36 */ |
| 467 | <0x00014000 0x00014000 0x001000>, /* ap 37 */ |
| 468 | <0x00015000 0x00015000 0x001000>; /* ap 38 */ |
| 469 | |
| 470 | target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ |
| 471 | compatible = "ti,sysc"; |
| 472 | status = "disabled"; |
| 473 | #address-cells = <1>; |
| 474 | #size-cells = <1>; |
| 475 | ranges = <0x0 0xc000 0x1000>; |
| 476 | }; |
| 477 | |
| 478 | target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ |
| 479 | compatible = "ti,sysc"; |
| 480 | status = "disabled"; |
| 481 | #address-cells = <1>; |
| 482 | #size-cells = <1>; |
| 483 | ranges = <0x0 0xe000 0x1000>; |
| 484 | }; |
| 485 | |
| 486 | target-module@10000 { /* 0x47c10000, ap 7 20.0 */ |
| 487 | compatible = "ti,sysc"; |
| 488 | status = "disabled"; |
| 489 | #address-cells = <1>; |
| 490 | #size-cells = <1>; |
| 491 | ranges = <0x0 0x10000 0x1000>; |
| 492 | }; |
| 493 | |
| 494 | target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ |
| 495 | compatible = "ti,sysc"; |
| 496 | status = "disabled"; |
| 497 | #address-cells = <1>; |
| 498 | #size-cells = <1>; |
| 499 | ranges = <0x0 0x14000 0x1000>; |
| 500 | }; |
| 501 | |
| 502 | target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ |
| 503 | compatible = "ti,sysc"; |
| 504 | status = "disabled"; |
| 505 | #address-cells = <1>; |
| 506 | #size-cells = <1>; |
| 507 | ranges = <0x0 0x1a000 0x1000>; |
| 508 | }; |
| 509 | |
| 510 | target-module@24000 { /* 0x47c24000, ap 11 28.0 */ |
| 511 | compatible = "ti,sysc"; |
| 512 | status = "disabled"; |
| 513 | #address-cells = <1>; |
| 514 | #size-cells = <1>; |
| 515 | ranges = <0x0 0x24000 0x1000>; |
| 516 | }; |
| 517 | |
| 518 | target-module@26000 { /* 0x47c26000, ap 13 30.0 */ |
| 519 | compatible = "ti,sysc"; |
| 520 | status = "disabled"; |
| 521 | #address-cells = <1>; |
| 522 | #size-cells = <1>; |
| 523 | ranges = <0x0 0x26000 0x1000>; |
| 524 | }; |
| 525 | |
| 526 | target-module@28000 { /* 0x47c28000, ap 29 40.0 */ |
| 527 | compatible = "ti,sysc"; |
| 528 | status = "disabled"; |
| 529 | #address-cells = <1>; |
| 530 | #size-cells = <1>; |
| 531 | ranges = <0x0 0x28000 0x1000>; |
| 532 | }; |
| 533 | |
| 534 | target-module@30000 { /* 0x47c30000, ap 15 14.0 */ |
| 535 | compatible = "ti,sysc"; |
| 536 | status = "disabled"; |
| 537 | #address-cells = <1>; |
| 538 | #size-cells = <1>; |
| 539 | ranges = <0x0 0x30000 0x1000>; |
| 540 | }; |
| 541 | |
| 542 | target-module@32000 { /* 0x47c32000, ap 31 06.0 */ |
| 543 | compatible = "ti,sysc"; |
| 544 | status = "disabled"; |
| 545 | #address-cells = <1>; |
| 546 | #size-cells = <1>; |
| 547 | ranges = <0x0 0x32000 0x1000>; |
| 548 | }; |
| 549 | |
| 550 | target-module@38000 { /* 0x47c38000, ap 17 18.0 */ |
| 551 | compatible = "ti,sysc"; |
| 552 | status = "disabled"; |
| 553 | #address-cells = <1>; |
| 554 | #size-cells = <1>; |
| 555 | ranges = <0x0 0x38000 0x1000>; |
| 556 | }; |
| 557 | |
| 558 | target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ |
| 559 | compatible = "ti,sysc"; |
| 560 | status = "disabled"; |
| 561 | #address-cells = <1>; |
| 562 | #size-cells = <1>; |
| 563 | ranges = <0x0 0x3a000 0x1000>; |
| 564 | }; |
| 565 | |
| 566 | target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ |
| 567 | compatible = "ti,sysc"; |
| 568 | status = "disabled"; |
| 569 | #address-cells = <1>; |
| 570 | #size-cells = <1>; |
| 571 | ranges = <0x0 0x3c000 0x1000>; |
| 572 | }; |
| 573 | |
| 574 | target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ |
| 575 | compatible = "ti,sysc"; |
| 576 | status = "disabled"; |
| 577 | #address-cells = <1>; |
| 578 | #size-cells = <1>; |
| 579 | ranges = <0x0 0x3e000 0x1000>; |
| 580 | }; |
| 581 | |
| 582 | target-module@40000 { /* 0x47c40000, ap 24 02.0 */ |
| 583 | compatible = "ti,sysc"; |
| 584 | status = "disabled"; |
| 585 | #address-cells = <1>; |
| 586 | #size-cells = <1>; |
| 587 | ranges = <0x0 0x40000 0x1000>; |
| 588 | }; |
| 589 | |
| 590 | target-module@42000 { /* 0x47c42000, ap 35 34.0 */ |
| 591 | compatible = "ti,sysc"; |
| 592 | status = "disabled"; |
| 593 | #address-cells = <1>; |
| 594 | #size-cells = <1>; |
| 595 | ranges = <0x0 0x42000 0x1000>; |
| 596 | }; |
| 597 | |
| 598 | target-module@44000 { /* 0x47c44000, ap 27 24.0 */ |
| 599 | compatible = "ti,sysc"; |
| 600 | status = "disabled"; |
| 601 | #address-cells = <1>; |
| 602 | #size-cells = <1>; |
| 603 | ranges = <0x0 0x44000 0x1000>; |
| 604 | }; |
| 605 | |
| 606 | target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ |
| 607 | compatible = "ti,sysc"; |
| 608 | status = "disabled"; |
| 609 | #address-cells = <1>; |
| 610 | #size-cells = <1>; |
| 611 | ranges = <0x0 0x46000 0x1000>; |
| 612 | }; |
| 613 | }; |
| 614 | }; |
| 615 | |
| 616 | &l4_fast { /* 0x4a000000 */ |
| 617 | compatible = "ti,am33xx-l4-fast", "simple-bus"; |
| 618 | reg = <0x4a000000 0x800>, |
| 619 | <0x4a000800 0x800>, |
| 620 | <0x4a001000 0x400>; |
| 621 | reg-names = "ap", "la", "ia0"; |
| 622 | #address-cells = <1>; |
| 623 | #size-cells = <1>; |
| 624 | ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ |
| 625 | |
| 626 | segment@0 { /* 0x4a000000 */ |
| 627 | compatible = "simple-bus"; |
| 628 | #address-cells = <1>; |
| 629 | #size-cells = <1>; |
| 630 | ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ |
| 631 | <0x00000800 0x00000800 0x000800>, /* ap 1 */ |
| 632 | <0x00001000 0x00001000 0x000400>, /* ap 2 */ |
| 633 | <0x00100000 0x00100000 0x008000>, /* ap 3 */ |
| 634 | <0x00108000 0x00108000 0x001000>, /* ap 4 */ |
| 635 | <0x00180000 0x00180000 0x020000>, /* ap 5 */ |
| 636 | <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ |
| 637 | <0x00200000 0x00200000 0x080000>, /* ap 7 */ |
| 638 | <0x00280000 0x00280000 0x001000>, /* ap 8 */ |
| 639 | <0x00300000 0x00300000 0x080000>, /* ap 9 */ |
| 640 | <0x00380000 0x00380000 0x001000>; /* ap 10 */ |
| 641 | |
| 642 | target-module@100000 { /* 0x4a100000, ap 3 08.0 */ |
| 643 | compatible = "ti,sysc-omap4-simple", "ti,sysc"; |
| 644 | reg = <0x101200 0x4>, |
| 645 | <0x101208 0x4>, |
| 646 | <0x101204 0x4>; |
| 647 | reg-names = "rev", "sysc", "syss"; |
| 648 | ti,sysc-mask = <0>; |
| 649 | ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| 650 | <SYSC_IDLE_NO>; |
| 651 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 652 | <SYSC_IDLE_NO>; |
| 653 | ti,syss-mask = <1>; |
| 654 | clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; |
| 655 | clock-names = "fck"; |
| 656 | #address-cells = <1>; |
| 657 | #size-cells = <1>; |
| 658 | ranges = <0x0 0x100000 0x8000>; |
| 659 | }; |
| 660 | |
| 661 | target-module@180000 { /* 0x4a180000, ap 5 10.0 */ |
| 662 | compatible = "ti,sysc"; |
| 663 | status = "disabled"; |
| 664 | #address-cells = <1>; |
| 665 | #size-cells = <1>; |
| 666 | ranges = <0x0 0x180000 0x20000>; |
| 667 | }; |
| 668 | |
| 669 | target-module@200000 { /* 0x4a200000, ap 7 02.0 */ |
| 670 | compatible = "ti,sysc"; |
| 671 | status = "disabled"; |
| 672 | #address-cells = <1>; |
| 673 | #size-cells = <1>; |
| 674 | ranges = <0x0 0x200000 0x80000>; |
| 675 | }; |
| 676 | |
| 677 | pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ |
| 678 | compatible = "ti,sysc-pruss", "ti,sysc"; |
| 679 | reg = <0x326000 0x4>, |
| 680 | <0x326004 0x4>; |
| 681 | reg-names = "rev", "sysc"; |
| 682 | ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | |
| 683 | SYSC_PRUSS_SUB_MWAIT)>; |
| 684 | ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| 685 | <SYSC_IDLE_NO>, |
| 686 | <SYSC_IDLE_SMART>; |
| 687 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 688 | <SYSC_IDLE_NO>, |
| 689 | <SYSC_IDLE_SMART>; |
| 690 | clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>; |
| 691 | clock-names = "fck"; |
| 692 | resets = <&prm_per 1>; |
| 693 | reset-names = "rstctrl"; |
| 694 | #address-cells = <1>; |
| 695 | #size-cells = <1>; |
| 696 | ranges = <0x0 0x300000 0x80000>; |
| 697 | status = "disabled"; |
| 698 | }; |
| 699 | }; |
| 700 | }; |
| 701 | |
| 702 | &l4_mpuss { /* 0x4b140000 */ |
| 703 | compatible = "ti,am33xx-l4-mpuss", "simple-bus"; |
| 704 | reg = <0x4b144400 0x100>, |
| 705 | <0x4b144800 0x400>; |
| 706 | reg-names = "la", "ap"; |
| 707 | #address-cells = <1>; |
| 708 | #size-cells = <1>; |
| 709 | ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ |
| 710 | |
| 711 | segment@0 { /* 0x4b140000 */ |
| 712 | compatible = "simple-bus"; |
| 713 | #address-cells = <1>; |
| 714 | #size-cells = <1>; |
| 715 | ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ |
| 716 | <0x00001000 0x00001000 0x001000>, /* ap 1 */ |
| 717 | <0x00002000 0x00002000 0x001000>, /* ap 2 */ |
| 718 | <0x00004000 0x00004000 0x000400>, /* ap 3 */ |
| 719 | <0x00005000 0x00005000 0x000400>, /* ap 4 */ |
| 720 | <0x00000000 0x00000000 0x001000>, /* ap 5 */ |
| 721 | <0x00003000 0x00003000 0x001000>, /* ap 6 */ |
| 722 | <0x00000800 0x00000800 0x000800>; /* ap 7 */ |
| 723 | |
| 724 | target-module@0 { /* 0x4b140000, ap 5 02.2 */ |
| 725 | compatible = "ti,sysc"; |
| 726 | status = "disabled"; |
| 727 | #address-cells = <1>; |
| 728 | #size-cells = <1>; |
| 729 | ranges = <0x00000000 0x00000000 0x00001000>, |
| 730 | <0x00001000 0x00001000 0x00001000>, |
| 731 | <0x00002000 0x00002000 0x00001000>; |
| 732 | }; |
| 733 | |
| 734 | target-module@3000 { /* 0x4b143000, ap 6 04.0 */ |
| 735 | compatible = "ti,sysc"; |
| 736 | status = "disabled"; |
| 737 | #address-cells = <1>; |
| 738 | #size-cells = <1>; |
| 739 | ranges = <0x0 0x3000 0x1000>; |
| 740 | }; |
| 741 | }; |
| 742 | }; |
| 743 | |
| 744 | &l4_per { /* 0x48000000 */ |
| 745 | compatible = "ti,am33xx-l4-per", "simple-bus"; |
| 746 | reg = <0x48000000 0x800>, |
| 747 | <0x48000800 0x800>, |
| 748 | <0x48001000 0x400>, |
| 749 | <0x48001400 0x400>, |
| 750 | <0x48001800 0x400>, |
| 751 | <0x48001c00 0x400>; |
| 752 | reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; |
| 753 | #address-cells = <1>; |
| 754 | #size-cells = <1>; |
| 755 | ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ |
| 756 | <0x00100000 0x48100000 0x100000>, /* segment 1 */ |
| 757 | <0x00200000 0x48200000 0x100000>, /* segment 2 */ |
| 758 | <0x00300000 0x48300000 0x100000>, /* segment 3 */ |
| 759 | <0x46000000 0x46000000 0x400000>, /* l3 data port */ |
| 760 | <0x46400000 0x46400000 0x400000>; /* l3 data port */ |
| 761 | |
| 762 | segment@0 { /* 0x48000000 */ |
| 763 | compatible = "simple-bus"; |
| 764 | #address-cells = <1>; |
| 765 | #size-cells = <1>; |
| 766 | ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ |
| 767 | <0x00000800 0x00000800 0x000800>, /* ap 1 */ |
| 768 | <0x00001000 0x00001000 0x000400>, /* ap 2 */ |
| 769 | <0x00001400 0x00001400 0x000400>, /* ap 3 */ |
| 770 | <0x00001800 0x00001800 0x000400>, /* ap 4 */ |
| 771 | <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ |
| 772 | <0x00008000 0x00008000 0x001000>, /* ap 6 */ |
| 773 | <0x00009000 0x00009000 0x001000>, /* ap 7 */ |
| 774 | <0x00016000 0x00016000 0x001000>, /* ap 8 */ |
| 775 | <0x00017000 0x00017000 0x001000>, /* ap 9 */ |
| 776 | <0x00022000 0x00022000 0x001000>, /* ap 10 */ |
| 777 | <0x00023000 0x00023000 0x001000>, /* ap 11 */ |
| 778 | <0x00024000 0x00024000 0x001000>, /* ap 12 */ |
| 779 | <0x00025000 0x00025000 0x001000>, /* ap 13 */ |
| 780 | <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ |
| 781 | <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ |
| 782 | <0x00038000 0x00038000 0x002000>, /* ap 16 */ |
| 783 | <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ |
| 784 | <0x00014000 0x00014000 0x001000>, /* ap 18 */ |
| 785 | <0x00015000 0x00015000 0x001000>, /* ap 19 */ |
| 786 | <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ |
| 787 | <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ |
| 788 | <0x00040000 0x00040000 0x001000>, /* ap 22 */ |
| 789 | <0x00041000 0x00041000 0x001000>, /* ap 23 */ |
| 790 | <0x00042000 0x00042000 0x001000>, /* ap 24 */ |
| 791 | <0x00043000 0x00043000 0x001000>, /* ap 25 */ |
| 792 | <0x00044000 0x00044000 0x001000>, /* ap 26 */ |
| 793 | <0x00045000 0x00045000 0x001000>, /* ap 27 */ |
| 794 | <0x00046000 0x00046000 0x001000>, /* ap 28 */ |
| 795 | <0x00047000 0x00047000 0x001000>, /* ap 29 */ |
| 796 | <0x00048000 0x00048000 0x001000>, /* ap 30 */ |
| 797 | <0x00049000 0x00049000 0x001000>, /* ap 31 */ |
| 798 | <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ |
| 799 | <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ |
| 800 | <0x00050000 0x00050000 0x002000>, /* ap 34 */ |
| 801 | <0x00052000 0x00052000 0x001000>, /* ap 35 */ |
| 802 | <0x00060000 0x00060000 0x001000>, /* ap 36 */ |
| 803 | <0x00061000 0x00061000 0x001000>, /* ap 37 */ |
| 804 | <0x00080000 0x00080000 0x010000>, /* ap 38 */ |
| 805 | <0x00090000 0x00090000 0x001000>, /* ap 39 */ |
| 806 | <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ |
| 807 | <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ |
| 808 | <0x00030000 0x00030000 0x001000>, /* ap 77 */ |
| 809 | <0x00031000 0x00031000 0x001000>, /* ap 78 */ |
| 810 | <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ |
| 811 | <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ |
| 812 | <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ |
| 813 | <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ |
| 814 | <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ |
| 815 | <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ |
| 816 | <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ |
| 817 | <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ |
| 818 | <0x46000000 0x46000000 0x400000>, /* l3 data port */ |
| 819 | <0x46400000 0x46400000 0x400000>; /* l3 data port */ |
| 820 | |
| 821 | target-module@8000 { /* 0x48008000, ap 6 10.0 */ |
| 822 | compatible = "ti,sysc"; |
| 823 | status = "disabled"; |
| 824 | #address-cells = <1>; |
| 825 | #size-cells = <1>; |
| 826 | ranges = <0x0 0x8000 0x1000>; |
| 827 | }; |
| 828 | |
| 829 | target-module@14000 { /* 0x48014000, ap 18 58.0 */ |
| 830 | compatible = "ti,sysc"; |
| 831 | status = "disabled"; |
| 832 | #address-cells = <1>; |
| 833 | #size-cells = <1>; |
| 834 | ranges = <0x0 0x14000 0x1000>; |
| 835 | }; |
| 836 | |
| 837 | target-module@16000 { /* 0x48016000, ap 8 3c.0 */ |
| 838 | compatible = "ti,sysc"; |
| 839 | status = "disabled"; |
| 840 | #address-cells = <1>; |
| 841 | #size-cells = <1>; |
| 842 | ranges = <0x0 0x16000 0x1000>; |
| 843 | }; |
| 844 | |
| 845 | target-module@22000 { /* 0x48022000, ap 10 12.0 */ |
| 846 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 847 | reg = <0x22050 0x4>, |
| 848 | <0x22054 0x4>, |
| 849 | <0x22058 0x4>; |
| 850 | reg-names = "rev", "sysc", "syss"; |
| 851 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| 852 | SYSC_OMAP2_SOFTRESET | |
| 853 | SYSC_OMAP2_AUTOIDLE)>; |
| 854 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 855 | <SYSC_IDLE_NO>, |
| 856 | <SYSC_IDLE_SMART>, |
| 857 | <SYSC_IDLE_SMART_WKUP>; |
| 858 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 859 | clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; |
| 860 | clock-names = "fck"; |
| 861 | #address-cells = <1>; |
| 862 | #size-cells = <1>; |
| 863 | ranges = <0x0 0x22000 0x1000>; |
| 864 | |
| 865 | uart1: serial@0 { |
| 866 | compatible = "ti,am3352-uart", "ti,omap3-uart"; |
| 867 | clock-frequency = <48000000>; |
| 868 | reg = <0x0 0x1000>; |
| 869 | interrupts = <73>; |
| 870 | status = "disabled"; |
| 871 | dmas = <&edma 28 0>, <&edma 29 0>; |
| 872 | dma-names = "tx", "rx"; |
| 873 | }; |
| 874 | }; |
| 875 | |
| 876 | target-module@24000 { /* 0x48024000, ap 12 14.0 */ |
| 877 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 878 | reg = <0x24050 0x4>, |
| 879 | <0x24054 0x4>, |
| 880 | <0x24058 0x4>; |
| 881 | reg-names = "rev", "sysc", "syss"; |
| 882 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| 883 | SYSC_OMAP2_SOFTRESET | |
| 884 | SYSC_OMAP2_AUTOIDLE)>; |
| 885 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 886 | <SYSC_IDLE_NO>, |
| 887 | <SYSC_IDLE_SMART>, |
| 888 | <SYSC_IDLE_SMART_WKUP>; |
| 889 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 890 | clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; |
| 891 | clock-names = "fck"; |
| 892 | #address-cells = <1>; |
| 893 | #size-cells = <1>; |
| 894 | ranges = <0x0 0x24000 0x1000>; |
| 895 | |
| 896 | uart2: serial@0 { |
| 897 | compatible = "ti,am3352-uart", "ti,omap3-uart"; |
| 898 | clock-frequency = <48000000>; |
| 899 | reg = <0x0 0x1000>; |
| 900 | interrupts = <74>; |
| 901 | status = "disabled"; |
| 902 | dmas = <&edma 30 0>, <&edma 31 0>; |
| 903 | dma-names = "tx", "rx"; |
| 904 | }; |
| 905 | }; |
| 906 | |
| 907 | target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ |
| 908 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 909 | reg = <0x2a000 0x8>, |
| 910 | <0x2a010 0x8>, |
| 911 | <0x2a090 0x8>; |
| 912 | reg-names = "rev", "sysc", "syss"; |
| 913 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| 914 | SYSC_OMAP2_ENAWAKEUP | |
| 915 | SYSC_OMAP2_SOFTRESET | |
| 916 | SYSC_OMAP2_AUTOIDLE)>; |
| 917 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 918 | <SYSC_IDLE_NO>, |
| 919 | <SYSC_IDLE_SMART>, |
| 920 | <SYSC_IDLE_SMART_WKUP>; |
| 921 | ti,syss-mask = <1>; |
| 922 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 923 | clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; |
| 924 | clock-names = "fck"; |
| 925 | #address-cells = <1>; |
| 926 | #size-cells = <1>; |
| 927 | ranges = <0x0 0x2a000 0x1000>; |
| 928 | }; |
| 929 | |
| 930 | target-module@30000 { /* 0x48030000, ap 77 08.0 */ |
| 931 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 932 | reg = <0x30000 0x4>, |
| 933 | <0x30110 0x4>, |
| 934 | <0x30114 0x4>; |
| 935 | reg-names = "rev", "sysc", "syss"; |
| 936 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| 937 | SYSC_OMAP2_SOFTRESET | |
| 938 | SYSC_OMAP2_AUTOIDLE)>; |
| 939 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 940 | <SYSC_IDLE_NO>, |
| 941 | <SYSC_IDLE_SMART>; |
| 942 | ti,syss-mask = <1>; |
| 943 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 944 | clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; |
| 945 | clock-names = "fck"; |
| 946 | #address-cells = <1>; |
| 947 | #size-cells = <1>; |
| 948 | ranges = <0x0 0x30000 0x1000>; |
| 949 | |
| 950 | spi0: spi@0 { |
| 951 | compatible = "ti,omap4-mcspi"; |
| 952 | #address-cells = <1>; |
| 953 | #size-cells = <0>; |
| 954 | reg = <0x0 0x400>; |
| 955 | interrupts = <65>; |
| 956 | ti,spi-num-cs = <2>; |
| 957 | dmas = <&edma 16 0 |
| 958 | &edma 17 0 |
| 959 | &edma 18 0 |
| 960 | &edma 19 0>; |
| 961 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 962 | status = "disabled"; |
| 963 | }; |
| 964 | }; |
| 965 | |
| 966 | target-module@38000 { /* 0x48038000, ap 16 02.0 */ |
| 967 | compatible = "ti,sysc-omap4-simple", "ti,sysc"; |
| 968 | reg = <0x38000 0x4>, |
| 969 | <0x38004 0x4>; |
| 970 | reg-names = "rev", "sysc"; |
| 971 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 972 | <SYSC_IDLE_NO>, |
| 973 | <SYSC_IDLE_SMART>; |
| 974 | /* Domains (P, C): per_pwrdm, l3s_clkdm */ |
| 975 | clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; |
| 976 | clock-names = "fck"; |
| 977 | #address-cells = <1>; |
| 978 | #size-cells = <1>; |
| 979 | ranges = <0x0 0x38000 0x2000>, |
| 980 | <0x46000000 0x46000000 0x400000>; |
| 981 | |
| 982 | mcasp0: mcasp@0 { |
| 983 | compatible = "ti,am33xx-mcasp-audio"; |
| 984 | reg = <0x0 0x2000>, |
| 985 | <0x46000000 0x400000>; |
| 986 | reg-names = "mpu", "dat"; |
| 987 | interrupts = <80>, <81>; |
| 988 | interrupt-names = "tx", "rx"; |
| 989 | status = "disabled"; |
| 990 | dmas = <&edma 8 2>, |
| 991 | <&edma 9 2>; |
| 992 | dma-names = "tx", "rx"; |
| 993 | }; |
| 994 | }; |
| 995 | |
| 996 | target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ |
| 997 | compatible = "ti,sysc-omap4-simple", "ti,sysc"; |
| 998 | reg = <0x3c000 0x4>, |
| 999 | <0x3c004 0x4>; |
| 1000 | reg-names = "rev", "sysc"; |
| 1001 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1002 | <SYSC_IDLE_NO>, |
| 1003 | <SYSC_IDLE_SMART>; |
| 1004 | /* Domains (P, C): per_pwrdm, l3s_clkdm */ |
| 1005 | clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; |
| 1006 | clock-names = "fck"; |
| 1007 | #address-cells = <1>; |
| 1008 | #size-cells = <1>; |
| 1009 | ranges = <0x0 0x3c000 0x2000>, |
| 1010 | <0x46400000 0x46400000 0x400000>; |
| 1011 | |
| 1012 | mcasp1: mcasp@0 { |
| 1013 | compatible = "ti,am33xx-mcasp-audio"; |
| 1014 | reg = <0x0 0x2000>, |
| 1015 | <0x46400000 0x400000>; |
| 1016 | reg-names = "mpu", "dat"; |
| 1017 | interrupts = <82>, <83>; |
| 1018 | interrupt-names = "tx", "rx"; |
| 1019 | status = "disabled"; |
| 1020 | dmas = <&edma 10 2>, |
| 1021 | <&edma 11 2>; |
| 1022 | dma-names = "tx", "rx"; |
| 1023 | }; |
| 1024 | }; |
| 1025 | |
| 1026 | timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */ |
| 1027 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| 1028 | reg = <0x40000 0x4>, |
| 1029 | <0x40010 0x4>, |
| 1030 | <0x40014 0x4>; |
| 1031 | reg-names = "rev", "sysc", "syss"; |
| 1032 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 1033 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1034 | <SYSC_IDLE_NO>, |
| 1035 | <SYSC_IDLE_SMART>, |
| 1036 | <SYSC_IDLE_SMART_WKUP>; |
| 1037 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1038 | clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; |
| 1039 | clock-names = "fck"; |
| 1040 | #address-cells = <1>; |
| 1041 | #size-cells = <1>; |
| 1042 | ranges = <0x0 0x40000 0x1000>; |
| 1043 | |
| 1044 | timer2: timer@0 { |
| 1045 | compatible = "ti,am335x-timer"; |
| 1046 | reg = <0x0 0x400>; |
| 1047 | interrupts = <68>; |
| 1048 | clocks = <&timer2_fck>; |
| 1049 | clock-names = "fck"; |
| 1050 | }; |
| 1051 | }; |
| 1052 | |
| 1053 | target-module@42000 { /* 0x48042000, ap 24 1c.0 */ |
| 1054 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| 1055 | reg = <0x42000 0x4>, |
| 1056 | <0x42010 0x4>, |
| 1057 | <0x42014 0x4>; |
| 1058 | reg-names = "rev", "sysc", "syss"; |
| 1059 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 1060 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1061 | <SYSC_IDLE_NO>, |
| 1062 | <SYSC_IDLE_SMART>, |
| 1063 | <SYSC_IDLE_SMART_WKUP>; |
| 1064 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1065 | clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; |
| 1066 | clock-names = "fck"; |
| 1067 | #address-cells = <1>; |
| 1068 | #size-cells = <1>; |
| 1069 | ranges = <0x0 0x42000 0x1000>; |
| 1070 | |
| 1071 | timer3: timer@0 { |
| 1072 | compatible = "ti,am335x-timer"; |
| 1073 | reg = <0x0 0x400>; |
| 1074 | interrupts = <69>; |
| 1075 | }; |
| 1076 | }; |
| 1077 | |
| 1078 | target-module@44000 { /* 0x48044000, ap 26 26.0 */ |
| 1079 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| 1080 | reg = <0x44000 0x4>, |
| 1081 | <0x44010 0x4>, |
| 1082 | <0x44014 0x4>; |
| 1083 | reg-names = "rev", "sysc", "syss"; |
| 1084 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 1085 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1086 | <SYSC_IDLE_NO>, |
| 1087 | <SYSC_IDLE_SMART>, |
| 1088 | <SYSC_IDLE_SMART_WKUP>; |
| 1089 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1090 | clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; |
| 1091 | clock-names = "fck"; |
| 1092 | #address-cells = <1>; |
| 1093 | #size-cells = <1>; |
| 1094 | ranges = <0x0 0x44000 0x1000>; |
| 1095 | |
| 1096 | timer4: timer@0 { |
| 1097 | compatible = "ti,am335x-timer"; |
| 1098 | reg = <0x0 0x400>; |
| 1099 | interrupts = <92>; |
| 1100 | ti,timer-pwm; |
| 1101 | }; |
| 1102 | }; |
| 1103 | |
| 1104 | target-module@46000 { /* 0x48046000, ap 28 28.0 */ |
| 1105 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| 1106 | reg = <0x46000 0x4>, |
| 1107 | <0x46010 0x4>, |
| 1108 | <0x46014 0x4>; |
| 1109 | reg-names = "rev", "sysc", "syss"; |
| 1110 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 1111 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1112 | <SYSC_IDLE_NO>, |
| 1113 | <SYSC_IDLE_SMART>, |
| 1114 | <SYSC_IDLE_SMART_WKUP>; |
| 1115 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1116 | clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; |
| 1117 | clock-names = "fck"; |
| 1118 | #address-cells = <1>; |
| 1119 | #size-cells = <1>; |
| 1120 | ranges = <0x0 0x46000 0x1000>; |
| 1121 | |
| 1122 | timer5: timer@0 { |
| 1123 | compatible = "ti,am335x-timer"; |
| 1124 | reg = <0x0 0x400>; |
| 1125 | interrupts = <93>; |
| 1126 | ti,timer-pwm; |
| 1127 | }; |
| 1128 | }; |
| 1129 | |
| 1130 | target-module@48000 { /* 0x48048000, ap 30 22.0 */ |
| 1131 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| 1132 | reg = <0x48000 0x4>, |
| 1133 | <0x48010 0x4>, |
| 1134 | <0x48014 0x4>; |
| 1135 | reg-names = "rev", "sysc", "syss"; |
| 1136 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 1137 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1138 | <SYSC_IDLE_NO>, |
| 1139 | <SYSC_IDLE_SMART>, |
| 1140 | <SYSC_IDLE_SMART_WKUP>; |
| 1141 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1142 | clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; |
| 1143 | clock-names = "fck"; |
| 1144 | #address-cells = <1>; |
| 1145 | #size-cells = <1>; |
| 1146 | ranges = <0x0 0x48000 0x1000>; |
| 1147 | |
| 1148 | timer6: timer@0 { |
| 1149 | compatible = "ti,am335x-timer"; |
| 1150 | reg = <0x0 0x400>; |
| 1151 | interrupts = <94>; |
| 1152 | ti,timer-pwm; |
| 1153 | }; |
| 1154 | }; |
| 1155 | |
| 1156 | target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ |
| 1157 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| 1158 | reg = <0x4a000 0x4>, |
| 1159 | <0x4a010 0x4>, |
| 1160 | <0x4a014 0x4>; |
| 1161 | reg-names = "rev", "sysc", "syss"; |
| 1162 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 1163 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1164 | <SYSC_IDLE_NO>, |
| 1165 | <SYSC_IDLE_SMART>, |
| 1166 | <SYSC_IDLE_SMART_WKUP>; |
| 1167 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1168 | clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; |
| 1169 | clock-names = "fck"; |
| 1170 | #address-cells = <1>; |
| 1171 | #size-cells = <1>; |
| 1172 | ranges = <0x0 0x4a000 0x1000>; |
| 1173 | |
| 1174 | timer7: timer@0 { |
| 1175 | compatible = "ti,am335x-timer"; |
| 1176 | reg = <0x0 0x400>; |
| 1177 | interrupts = <95>; |
| 1178 | ti,timer-pwm; |
| 1179 | }; |
| 1180 | }; |
| 1181 | |
| 1182 | target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ |
| 1183 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1184 | reg = <0x4c000 0x4>, |
| 1185 | <0x4c010 0x4>, |
| 1186 | <0x4c114 0x4>; |
| 1187 | reg-names = "rev", "sysc", "syss"; |
| 1188 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| 1189 | SYSC_OMAP2_SOFTRESET | |
| 1190 | SYSC_OMAP2_AUTOIDLE)>; |
| 1191 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1192 | <SYSC_IDLE_NO>, |
| 1193 | <SYSC_IDLE_SMART>, |
| 1194 | <SYSC_IDLE_SMART_WKUP>; |
| 1195 | ti,syss-mask = <1>; |
| 1196 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1197 | clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, |
| 1198 | <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; |
| 1199 | clock-names = "fck", "dbclk"; |
| 1200 | #address-cells = <1>; |
| 1201 | #size-cells = <1>; |
| 1202 | ranges = <0x0 0x4c000 0x1000>; |
| 1203 | }; |
| 1204 | |
| 1205 | target-module@50000 { /* 0x48050000, ap 34 2c.0 */ |
| 1206 | compatible = "ti,sysc"; |
| 1207 | status = "disabled"; |
| 1208 | #address-cells = <1>; |
| 1209 | #size-cells = <1>; |
| 1210 | ranges = <0x0 0x50000 0x2000>; |
| 1211 | }; |
| 1212 | |
| 1213 | target-module@60000 { /* 0x48060000, ap 36 0c.0 */ |
| 1214 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1215 | reg = <0x602fc 0x4>, |
| 1216 | <0x60110 0x4>, |
| 1217 | <0x60114 0x4>; |
| 1218 | reg-names = "rev", "sysc", "syss"; |
| 1219 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| 1220 | SYSC_OMAP2_ENAWAKEUP | |
| 1221 | SYSC_OMAP2_SOFTRESET | |
| 1222 | SYSC_OMAP2_AUTOIDLE)>; |
| 1223 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1224 | <SYSC_IDLE_NO>, |
| 1225 | <SYSC_IDLE_SMART>; |
| 1226 | ti,syss-mask = <1>; |
| 1227 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1228 | clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; |
| 1229 | clock-names = "fck"; |
| 1230 | #address-cells = <1>; |
| 1231 | #size-cells = <1>; |
| 1232 | ranges = <0x0 0x60000 0x1000>; |
| 1233 | }; |
| 1234 | |
| 1235 | target-module@80000 { /* 0x48080000, ap 38 18.0 */ |
| 1236 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1237 | reg = <0x80000 0x4>, |
| 1238 | <0x80010 0x4>, |
| 1239 | <0x80014 0x4>; |
| 1240 | reg-names = "rev", "sysc", "syss"; |
| 1241 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| 1242 | SYSC_OMAP2_SOFTRESET | |
| 1243 | SYSC_OMAP2_AUTOIDLE)>; |
| 1244 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1245 | <SYSC_IDLE_NO>, |
| 1246 | <SYSC_IDLE_SMART>; |
| 1247 | ti,syss-mask = <1>; |
| 1248 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1249 | clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; |
| 1250 | clock-names = "fck"; |
| 1251 | #address-cells = <1>; |
| 1252 | #size-cells = <1>; |
| 1253 | ranges = <0x0 0x80000 0x10000>; |
| 1254 | |
| 1255 | elm: elm@0 { |
| 1256 | compatible = "ti,am3352-elm"; |
| 1257 | reg = <0x0 0x2000>; |
| 1258 | interrupts = <4>; |
| 1259 | status = "disabled"; |
| 1260 | }; |
| 1261 | }; |
| 1262 | |
| 1263 | target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ |
| 1264 | compatible = "ti,sysc"; |
| 1265 | status = "disabled"; |
| 1266 | #address-cells = <1>; |
| 1267 | #size-cells = <1>; |
| 1268 | ranges = <0x0 0xa0000 0x10000>; |
| 1269 | }; |
| 1270 | |
| 1271 | target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ |
| 1272 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 1273 | reg = <0xc8000 0x4>, |
| 1274 | <0xc8010 0x4>; |
| 1275 | reg-names = "rev", "sysc"; |
| 1276 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 1277 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1278 | <SYSC_IDLE_NO>, |
| 1279 | <SYSC_IDLE_SMART>; |
| 1280 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1281 | clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; |
| 1282 | clock-names = "fck"; |
| 1283 | #address-cells = <1>; |
| 1284 | #size-cells = <1>; |
| 1285 | ranges = <0x0 0xc8000 0x1000>; |
| 1286 | |
| 1287 | mailbox: mailbox@0 { |
| 1288 | compatible = "ti,omap4-mailbox"; |
| 1289 | reg = <0x0 0x200>; |
| 1290 | interrupts = <77>; |
| 1291 | #mbox-cells = <1>; |
| 1292 | ti,mbox-num-users = <4>; |
| 1293 | ti,mbox-num-fifos = <8>; |
| 1294 | mbox_wkupm3: wkup_m3 { |
| 1295 | ti,mbox-send-noirq; |
| 1296 | ti,mbox-tx = <0 0 0>; |
| 1297 | ti,mbox-rx = <0 0 3>; |
| 1298 | }; |
| 1299 | }; |
| 1300 | }; |
| 1301 | |
| 1302 | target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ |
| 1303 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1304 | reg = <0xca000 0x4>, |
| 1305 | <0xca010 0x4>, |
| 1306 | <0xca014 0x4>; |
| 1307 | reg-names = "rev", "sysc", "syss"; |
| 1308 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| 1309 | SYSC_OMAP2_ENAWAKEUP | |
| 1310 | SYSC_OMAP2_SOFTRESET | |
| 1311 | SYSC_OMAP2_AUTOIDLE)>; |
| 1312 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1313 | <SYSC_IDLE_NO>, |
| 1314 | <SYSC_IDLE_SMART>; |
| 1315 | ti,syss-mask = <1>; |
| 1316 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1317 | clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; |
| 1318 | clock-names = "fck"; |
| 1319 | #address-cells = <1>; |
| 1320 | #size-cells = <1>; |
| 1321 | ranges = <0x0 0xca000 0x1000>; |
| 1322 | |
| 1323 | hwspinlock: spinlock@0 { |
| 1324 | compatible = "ti,omap4-hwspinlock"; |
| 1325 | reg = <0x0 0x1000>; |
| 1326 | #hwlock-cells = <1>; |
| 1327 | }; |
| 1328 | }; |
| 1329 | |
| 1330 | target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ |
| 1331 | compatible = "ti,sysc"; |
| 1332 | status = "disabled"; |
| 1333 | #address-cells = <1>; |
| 1334 | #size-cells = <1>; |
| 1335 | ranges = <0x0 0xcc000 0x1000>; |
| 1336 | }; |
| 1337 | }; |
| 1338 | |
| 1339 | segment@100000 { /* 0x48100000 */ |
| 1340 | compatible = "simple-bus"; |
| 1341 | #address-cells = <1>; |
| 1342 | #size-cells = <1>; |
| 1343 | ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ |
| 1344 | <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ |
| 1345 | <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ |
| 1346 | <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ |
| 1347 | <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ |
| 1348 | <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ |
| 1349 | <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ |
| 1350 | <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ |
| 1351 | <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ |
| 1352 | <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ |
| 1353 | <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ |
| 1354 | <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ |
| 1355 | <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ |
| 1356 | <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ |
| 1357 | <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ |
| 1358 | <0x000af000 0x001af000 0x001000>, /* ap 57 */ |
| 1359 | <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ |
| 1360 | <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ |
| 1361 | <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ |
| 1362 | <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ |
| 1363 | <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ |
| 1364 | <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ |
| 1365 | <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ |
| 1366 | <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ |
| 1367 | <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ |
| 1368 | <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ |
| 1369 | <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ |
| 1370 | <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ |
| 1371 | <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ |
| 1372 | <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ |
| 1373 | |
| 1374 | target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ |
| 1375 | compatible = "ti,sysc"; |
| 1376 | status = "disabled"; |
| 1377 | #address-cells = <1>; |
| 1378 | #size-cells = <1>; |
| 1379 | ranges = <0x0 0x8c000 0x1000>; |
| 1380 | }; |
| 1381 | |
| 1382 | target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ |
| 1383 | compatible = "ti,sysc"; |
| 1384 | status = "disabled"; |
| 1385 | #address-cells = <1>; |
| 1386 | #size-cells = <1>; |
| 1387 | ranges = <0x0 0x8e000 0x1000>; |
| 1388 | }; |
| 1389 | |
| 1390 | target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ |
| 1391 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1392 | reg = <0x9c000 0x8>, |
| 1393 | <0x9c010 0x8>, |
| 1394 | <0x9c090 0x8>; |
| 1395 | reg-names = "rev", "sysc", "syss"; |
| 1396 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| 1397 | SYSC_OMAP2_ENAWAKEUP | |
| 1398 | SYSC_OMAP2_SOFTRESET | |
| 1399 | SYSC_OMAP2_AUTOIDLE)>; |
| 1400 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1401 | <SYSC_IDLE_NO>, |
| 1402 | <SYSC_IDLE_SMART>, |
| 1403 | <SYSC_IDLE_SMART_WKUP>; |
| 1404 | ti,syss-mask = <1>; |
| 1405 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1406 | clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; |
| 1407 | clock-names = "fck"; |
| 1408 | #address-cells = <1>; |
| 1409 | #size-cells = <1>; |
| 1410 | ranges = <0x0 0x9c000 0x1000>; |
| 1411 | }; |
| 1412 | |
| 1413 | target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ |
| 1414 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1415 | reg = <0xa0000 0x4>, |
| 1416 | <0xa0110 0x4>, |
| 1417 | <0xa0114 0x4>; |
| 1418 | reg-names = "rev", "sysc", "syss"; |
| 1419 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| 1420 | SYSC_OMAP2_SOFTRESET | |
| 1421 | SYSC_OMAP2_AUTOIDLE)>; |
| 1422 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1423 | <SYSC_IDLE_NO>, |
| 1424 | <SYSC_IDLE_SMART>; |
| 1425 | ti,syss-mask = <1>; |
| 1426 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1427 | clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; |
| 1428 | clock-names = "fck"; |
| 1429 | #address-cells = <1>; |
| 1430 | #size-cells = <1>; |
| 1431 | ranges = <0x0 0xa0000 0x1000>; |
| 1432 | |
| 1433 | spi1: spi@0 { |
| 1434 | compatible = "ti,omap4-mcspi"; |
| 1435 | #address-cells = <1>; |
| 1436 | #size-cells = <0>; |
| 1437 | reg = <0x0 0x400>; |
| 1438 | interrupts = <125>; |
| 1439 | ti,spi-num-cs = <2>; |
| 1440 | dmas = <&edma 42 0 |
| 1441 | &edma 43 0 |
| 1442 | &edma 44 0 |
| 1443 | &edma 45 0>; |
| 1444 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 1445 | status = "disabled"; |
| 1446 | }; |
| 1447 | }; |
| 1448 | |
| 1449 | target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ |
| 1450 | compatible = "ti,sysc"; |
| 1451 | status = "disabled"; |
| 1452 | #address-cells = <1>; |
| 1453 | #size-cells = <1>; |
| 1454 | ranges = <0x0 0xa2000 0x1000>; |
| 1455 | }; |
| 1456 | |
| 1457 | target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ |
| 1458 | compatible = "ti,sysc"; |
| 1459 | status = "disabled"; |
| 1460 | #address-cells = <1>; |
| 1461 | #size-cells = <1>; |
| 1462 | ranges = <0x0 0xa4000 0x1000>; |
| 1463 | }; |
| 1464 | |
| 1465 | target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ |
| 1466 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1467 | reg = <0xa6050 0x4>, |
| 1468 | <0xa6054 0x4>, |
| 1469 | <0xa6058 0x4>; |
| 1470 | reg-names = "rev", "sysc", "syss"; |
| 1471 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| 1472 | SYSC_OMAP2_SOFTRESET | |
| 1473 | SYSC_OMAP2_AUTOIDLE)>; |
| 1474 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1475 | <SYSC_IDLE_NO>, |
| 1476 | <SYSC_IDLE_SMART>, |
| 1477 | <SYSC_IDLE_SMART_WKUP>; |
| 1478 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1479 | clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; |
| 1480 | clock-names = "fck"; |
| 1481 | #address-cells = <1>; |
| 1482 | #size-cells = <1>; |
| 1483 | ranges = <0x0 0xa6000 0x1000>; |
| 1484 | |
| 1485 | uart3: serial@0 { |
| 1486 | compatible = "ti,am3352-uart", "ti,omap3-uart"; |
| 1487 | clock-frequency = <48000000>; |
| 1488 | reg = <0x0 0x1000>; |
| 1489 | interrupts = <44>; |
| 1490 | status = "disabled"; |
| 1491 | }; |
| 1492 | }; |
| 1493 | |
| 1494 | target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ |
| 1495 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1496 | reg = <0xa8050 0x4>, |
| 1497 | <0xa8054 0x4>, |
| 1498 | <0xa8058 0x4>; |
| 1499 | reg-names = "rev", "sysc", "syss"; |
| 1500 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| 1501 | SYSC_OMAP2_SOFTRESET | |
| 1502 | SYSC_OMAP2_AUTOIDLE)>; |
| 1503 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1504 | <SYSC_IDLE_NO>, |
| 1505 | <SYSC_IDLE_SMART>, |
| 1506 | <SYSC_IDLE_SMART_WKUP>; |
| 1507 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1508 | clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; |
| 1509 | clock-names = "fck"; |
| 1510 | #address-cells = <1>; |
| 1511 | #size-cells = <1>; |
| 1512 | ranges = <0x0 0xa8000 0x1000>; |
| 1513 | |
| 1514 | uart4: serial@0 { |
| 1515 | compatible = "ti,am3352-uart", "ti,omap3-uart"; |
| 1516 | clock-frequency = <48000000>; |
| 1517 | reg = <0x0 0x1000>; |
| 1518 | interrupts = <45>; |
| 1519 | status = "disabled"; |
| 1520 | }; |
| 1521 | }; |
| 1522 | |
| 1523 | target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ |
| 1524 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1525 | reg = <0xaa050 0x4>, |
| 1526 | <0xaa054 0x4>, |
| 1527 | <0xaa058 0x4>; |
| 1528 | reg-names = "rev", "sysc", "syss"; |
| 1529 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| 1530 | SYSC_OMAP2_SOFTRESET | |
| 1531 | SYSC_OMAP2_AUTOIDLE)>; |
| 1532 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1533 | <SYSC_IDLE_NO>, |
| 1534 | <SYSC_IDLE_SMART>, |
| 1535 | <SYSC_IDLE_SMART_WKUP>; |
| 1536 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1537 | clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; |
| 1538 | clock-names = "fck"; |
| 1539 | #address-cells = <1>; |
| 1540 | #size-cells = <1>; |
| 1541 | ranges = <0x0 0xaa000 0x1000>; |
| 1542 | |
| 1543 | uart5: serial@0 { |
| 1544 | compatible = "ti,am3352-uart", "ti,omap3-uart"; |
| 1545 | clock-frequency = <48000000>; |
| 1546 | reg = <0x0 0x1000>; |
| 1547 | interrupts = <46>; |
| 1548 | status = "disabled"; |
| 1549 | }; |
| 1550 | }; |
| 1551 | |
| 1552 | target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ |
| 1553 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1554 | reg = <0xac000 0x4>, |
| 1555 | <0xac010 0x4>, |
| 1556 | <0xac114 0x4>; |
| 1557 | reg-names = "rev", "sysc", "syss"; |
| 1558 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| 1559 | SYSC_OMAP2_SOFTRESET | |
| 1560 | SYSC_OMAP2_AUTOIDLE)>; |
| 1561 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1562 | <SYSC_IDLE_NO>, |
| 1563 | <SYSC_IDLE_SMART>, |
| 1564 | <SYSC_IDLE_SMART_WKUP>; |
| 1565 | ti,syss-mask = <1>; |
| 1566 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1567 | clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, |
| 1568 | <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; |
| 1569 | clock-names = "fck", "dbclk"; |
| 1570 | #address-cells = <1>; |
| 1571 | #size-cells = <1>; |
| 1572 | ranges = <0x0 0xac000 0x1000>; |
| 1573 | }; |
| 1574 | |
| 1575 | target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ |
| 1576 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1577 | reg = <0xae000 0x4>, |
| 1578 | <0xae010 0x4>, |
| 1579 | <0xae114 0x4>; |
| 1580 | reg-names = "rev", "sysc", "syss"; |
| 1581 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
| 1582 | SYSC_OMAP2_SOFTRESET | |
| 1583 | SYSC_OMAP2_AUTOIDLE)>; |
| 1584 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1585 | <SYSC_IDLE_NO>, |
| 1586 | <SYSC_IDLE_SMART>, |
| 1587 | <SYSC_IDLE_SMART_WKUP>; |
| 1588 | ti,syss-mask = <1>; |
| 1589 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1590 | clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, |
| 1591 | <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; |
| 1592 | clock-names = "fck", "dbclk"; |
| 1593 | #address-cells = <1>; |
| 1594 | #size-cells = <1>; |
| 1595 | ranges = <0x0 0xae000 0x1000>; |
| 1596 | }; |
| 1597 | |
| 1598 | target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ |
| 1599 | compatible = "ti,sysc"; |
| 1600 | status = "disabled"; |
| 1601 | #address-cells = <1>; |
| 1602 | #size-cells = <1>; |
| 1603 | ranges = <0x0 0xb0000 0x10000>; |
| 1604 | }; |
| 1605 | |
| 1606 | target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ |
| 1607 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 1608 | reg = <0xcc020 0x4>; |
| 1609 | reg-names = "rev"; |
| 1610 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1611 | clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, |
| 1612 | <&dcan0_fck>; |
| 1613 | clock-names = "fck", "osc"; |
| 1614 | #address-cells = <1>; |
| 1615 | #size-cells = <1>; |
| 1616 | ranges = <0x0 0xcc000 0x2000>; |
| 1617 | |
| 1618 | dcan0: can@0 { |
| 1619 | compatible = "ti,am3352-d_can"; |
| 1620 | reg = <0x0 0x2000>; |
| 1621 | clocks = <&dcan0_fck>; |
| 1622 | clock-names = "fck"; |
| 1623 | syscon-raminit = <&scm_conf 0x644 0>; |
| 1624 | interrupts = <52>; |
| 1625 | status = "disabled"; |
| 1626 | }; |
| 1627 | }; |
| 1628 | |
| 1629 | target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ |
| 1630 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 1631 | reg = <0xd0020 0x4>; |
| 1632 | reg-names = "rev"; |
| 1633 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1634 | clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>, |
| 1635 | <&dcan1_fck>; |
| 1636 | clock-names = "fck", "osc"; |
| 1637 | #address-cells = <1>; |
| 1638 | #size-cells = <1>; |
| 1639 | ranges = <0x0 0xd0000 0x2000>; |
| 1640 | |
| 1641 | dcan1: can@0 { |
| 1642 | compatible = "ti,am3352-d_can"; |
| 1643 | reg = <0x0 0x2000>; |
| 1644 | clocks = <&dcan1_fck>; |
| 1645 | clock-names = "fck"; |
| 1646 | syscon-raminit = <&scm_conf 0x644 1>; |
| 1647 | interrupts = <55>; |
| 1648 | status = "disabled"; |
| 1649 | }; |
| 1650 | }; |
| 1651 | |
| 1652 | target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ |
| 1653 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1654 | reg = <0xd82fc 0x4>, |
| 1655 | <0xd8110 0x4>, |
| 1656 | <0xd8114 0x4>; |
| 1657 | reg-names = "rev", "sysc", "syss"; |
| 1658 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| 1659 | SYSC_OMAP2_ENAWAKEUP | |
| 1660 | SYSC_OMAP2_SOFTRESET | |
| 1661 | SYSC_OMAP2_AUTOIDLE)>; |
| 1662 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1663 | <SYSC_IDLE_NO>, |
| 1664 | <SYSC_IDLE_SMART>; |
| 1665 | ti,syss-mask = <1>; |
| 1666 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1667 | clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; |
| 1668 | clock-names = "fck"; |
| 1669 | #address-cells = <1>; |
| 1670 | #size-cells = <1>; |
| 1671 | ranges = <0x0 0xd8000 0x1000>; |
| 1672 | }; |
| 1673 | }; |
| 1674 | |
| 1675 | segment@200000 { /* 0x48200000 */ |
| 1676 | compatible = "simple-bus"; |
| 1677 | #address-cells = <1>; |
| 1678 | #size-cells = <1>; |
| 1679 | }; |
| 1680 | |
| 1681 | segment@300000 { /* 0x48300000 */ |
| 1682 | compatible = "simple-bus"; |
| 1683 | #address-cells = <1>; |
| 1684 | #size-cells = <1>; |
| 1685 | ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ |
| 1686 | <0x00001000 0x00301000 0x001000>, /* ap 67 */ |
| 1687 | <0x00002000 0x00302000 0x001000>, /* ap 68 */ |
| 1688 | <0x00003000 0x00303000 0x001000>, /* ap 69 */ |
| 1689 | <0x00004000 0x00304000 0x001000>, /* ap 70 */ |
| 1690 | <0x00005000 0x00305000 0x001000>, /* ap 71 */ |
| 1691 | <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ |
| 1692 | <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ |
| 1693 | <0x00018000 0x00318000 0x004000>, /* ap 74 */ |
| 1694 | <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ |
| 1695 | <0x00010000 0x00310000 0x002000>, /* ap 76 */ |
| 1696 | <0x00012000 0x00312000 0x001000>, /* ap 93 */ |
| 1697 | <0x00015000 0x00315000 0x001000>, /* ap 94 */ |
| 1698 | <0x00016000 0x00316000 0x001000>, /* ap 95 */ |
| 1699 | <0x00017000 0x00317000 0x001000>, /* ap 96 */ |
| 1700 | <0x00013000 0x00313000 0x001000>, /* ap 97 */ |
| 1701 | <0x00014000 0x00314000 0x001000>, /* ap 98 */ |
| 1702 | <0x00020000 0x00320000 0x001000>, /* ap 99 */ |
| 1703 | <0x00021000 0x00321000 0x001000>, /* ap 100 */ |
| 1704 | <0x00022000 0x00322000 0x001000>, /* ap 101 */ |
| 1705 | <0x00023000 0x00323000 0x001000>, /* ap 102 */ |
| 1706 | <0x00024000 0x00324000 0x001000>, /* ap 103 */ |
| 1707 | <0x00025000 0x00325000 0x001000>; /* ap 104 */ |
| 1708 | |
| 1709 | target-module@0 { /* 0x48300000, ap 66 48.0 */ |
| 1710 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 1711 | reg = <0x0 0x4>, |
| 1712 | <0x4 0x4>; |
| 1713 | reg-names = "rev", "sysc"; |
| 1714 | ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| 1715 | <SYSC_IDLE_NO>, |
| 1716 | <SYSC_IDLE_SMART>, |
| 1717 | <SYSC_IDLE_SMART_WKUP>; |
| 1718 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1719 | <SYSC_IDLE_NO>, |
| 1720 | <SYSC_IDLE_SMART>, |
| 1721 | <SYSC_IDLE_SMART_WKUP>; |
| 1722 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1723 | clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; |
| 1724 | clock-names = "fck"; |
| 1725 | #address-cells = <1>; |
| 1726 | #size-cells = <1>; |
| 1727 | ranges = <0x0 0x0 0x1000>; |
| 1728 | |
| 1729 | epwmss0: epwmss@0 { |
| 1730 | compatible = "ti,am33xx-pwmss"; |
| 1731 | reg = <0x0 0x10>; |
| 1732 | #address-cells = <1>; |
| 1733 | #size-cells = <1>; |
| 1734 | status = "disabled"; |
| 1735 | ranges = <0 0 0x1000>; |
| 1736 | |
| 1737 | ecap0: ecap@100 { |
| 1738 | compatible = "ti,am3352-ecap", |
| 1739 | "ti,am33xx-ecap"; |
| 1740 | #pwm-cells = <3>; |
| 1741 | reg = <0x100 0x80>; |
| 1742 | clocks = <&l4ls_gclk>; |
| 1743 | clock-names = "fck"; |
| 1744 | interrupts = <31>; |
| 1745 | interrupt-names = "ecap0"; |
| 1746 | status = "disabled"; |
| 1747 | }; |
| 1748 | |
| 1749 | ehrpwm0: pwm@200 { |
| 1750 | compatible = "ti,am3352-ehrpwm", |
| 1751 | "ti,am33xx-ehrpwm"; |
| 1752 | #pwm-cells = <3>; |
| 1753 | reg = <0x200 0x80>; |
| 1754 | clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; |
| 1755 | clock-names = "tbclk", "fck"; |
| 1756 | status = "disabled"; |
| 1757 | }; |
| 1758 | }; |
| 1759 | }; |
| 1760 | |
| 1761 | target-module@2000 { /* 0x48302000, ap 68 52.0 */ |
| 1762 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 1763 | reg = <0x2000 0x4>, |
| 1764 | <0x2004 0x4>; |
| 1765 | reg-names = "rev", "sysc"; |
| 1766 | ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| 1767 | <SYSC_IDLE_NO>, |
| 1768 | <SYSC_IDLE_SMART>, |
| 1769 | <SYSC_IDLE_SMART_WKUP>; |
| 1770 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1771 | <SYSC_IDLE_NO>, |
| 1772 | <SYSC_IDLE_SMART>, |
| 1773 | <SYSC_IDLE_SMART_WKUP>; |
| 1774 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1775 | clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; |
| 1776 | clock-names = "fck"; |
| 1777 | #address-cells = <1>; |
| 1778 | #size-cells = <1>; |
| 1779 | ranges = <0x0 0x2000 0x1000>; |
| 1780 | |
| 1781 | epwmss1: epwmss@0 { |
| 1782 | compatible = "ti,am33xx-pwmss"; |
| 1783 | reg = <0x0 0x10>; |
| 1784 | #address-cells = <1>; |
| 1785 | #size-cells = <1>; |
| 1786 | status = "disabled"; |
| 1787 | ranges = <0 0 0x1000>; |
| 1788 | |
| 1789 | ecap1: ecap@100 { |
| 1790 | compatible = "ti,am3352-ecap", |
| 1791 | "ti,am33xx-ecap"; |
| 1792 | #pwm-cells = <3>; |
| 1793 | reg = <0x100 0x80>; |
| 1794 | clocks = <&l4ls_gclk>; |
| 1795 | clock-names = "fck"; |
| 1796 | interrupts = <47>; |
| 1797 | interrupt-names = "ecap1"; |
| 1798 | status = "disabled"; |
| 1799 | }; |
| 1800 | |
| 1801 | ehrpwm1: pwm@200 { |
| 1802 | compatible = "ti,am3352-ehrpwm", |
| 1803 | "ti,am33xx-ehrpwm"; |
| 1804 | #pwm-cells = <3>; |
| 1805 | reg = <0x200 0x80>; |
| 1806 | clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; |
| 1807 | clock-names = "tbclk", "fck"; |
| 1808 | status = "disabled"; |
| 1809 | }; |
| 1810 | }; |
| 1811 | }; |
| 1812 | |
| 1813 | target-module@4000 { /* 0x48304000, ap 70 44.0 */ |
| 1814 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 1815 | reg = <0x4000 0x4>, |
| 1816 | <0x4004 0x4>; |
| 1817 | reg-names = "rev", "sysc"; |
| 1818 | ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| 1819 | <SYSC_IDLE_NO>, |
| 1820 | <SYSC_IDLE_SMART>, |
| 1821 | <SYSC_IDLE_SMART_WKUP>; |
| 1822 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1823 | <SYSC_IDLE_NO>, |
| 1824 | <SYSC_IDLE_SMART>, |
| 1825 | <SYSC_IDLE_SMART_WKUP>; |
| 1826 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1827 | clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; |
| 1828 | clock-names = "fck"; |
| 1829 | #address-cells = <1>; |
| 1830 | #size-cells = <1>; |
| 1831 | ranges = <0x0 0x4000 0x1000>; |
| 1832 | |
| 1833 | epwmss2: epwmss@0 { |
| 1834 | compatible = "ti,am33xx-pwmss"; |
| 1835 | reg = <0x0 0x10>; |
| 1836 | #address-cells = <1>; |
| 1837 | #size-cells = <1>; |
| 1838 | status = "disabled"; |
| 1839 | ranges = <0 0 0x1000>; |
| 1840 | |
| 1841 | ecap2: ecap@100 { |
| 1842 | compatible = "ti,am3352-ecap", |
| 1843 | "ti,am33xx-ecap"; |
| 1844 | #pwm-cells = <3>; |
| 1845 | reg = <0x100 0x80>; |
| 1846 | clocks = <&l4ls_gclk>; |
| 1847 | clock-names = "fck"; |
| 1848 | interrupts = <61>; |
| 1849 | interrupt-names = "ecap2"; |
| 1850 | status = "disabled"; |
| 1851 | }; |
| 1852 | |
| 1853 | ehrpwm2: pwm@200 { |
| 1854 | compatible = "ti,am3352-ehrpwm", |
| 1855 | "ti,am33xx-ehrpwm"; |
| 1856 | #pwm-cells = <3>; |
| 1857 | reg = <0x200 0x80>; |
| 1858 | clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; |
| 1859 | clock-names = "tbclk", "fck"; |
| 1860 | status = "disabled"; |
| 1861 | }; |
| 1862 | }; |
| 1863 | }; |
| 1864 | |
| 1865 | target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ |
| 1866 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 1867 | reg = <0xe000 0x4>, |
| 1868 | <0xe054 0x4>; |
| 1869 | reg-names = "rev", "sysc"; |
| 1870 | ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| 1871 | <SYSC_IDLE_NO>, |
| 1872 | <SYSC_IDLE_SMART>; |
| 1873 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1874 | <SYSC_IDLE_NO>, |
| 1875 | <SYSC_IDLE_SMART>; |
| 1876 | /* Domains (P, C): per_pwrdm, lcdc_clkdm */ |
| 1877 | clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; |
| 1878 | clock-names = "fck"; |
| 1879 | #address-cells = <1>; |
| 1880 | #size-cells = <1>; |
| 1881 | ranges = <0x0 0xe000 0x1000>; |
| 1882 | |
| 1883 | lcdc: lcdc@0 { |
| 1884 | compatible = "ti,am33xx-tilcdc"; |
| 1885 | reg = <0x0 0x1000>; |
| 1886 | interrupts = <36>; |
| 1887 | status = "disabled"; |
| 1888 | }; |
| 1889 | }; |
| 1890 | |
| 1891 | target-module@10000 { /* 0x48310000, ap 76 4e.1 */ |
| 1892 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1893 | reg = <0x11fe0 0x4>, |
| 1894 | <0x11fe4 0x4>; |
| 1895 | reg-names = "rev", "sysc"; |
| 1896 | ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; |
| 1897 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1898 | <SYSC_IDLE_NO>; |
| 1899 | /* Domains (P, C): per_pwrdm, l4ls_clkdm */ |
| 1900 | clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; |
| 1901 | clock-names = "fck"; |
| 1902 | #address-cells = <1>; |
| 1903 | #size-cells = <1>; |
| 1904 | ranges = <0x0 0x10000 0x2000>; |
| 1905 | |
| 1906 | rng: rng@0 { |
| 1907 | compatible = "ti,omap4-rng"; |
| 1908 | reg = <0x0 0x2000>; |
| 1909 | interrupts = <111>; |
| 1910 | }; |
| 1911 | }; |
| 1912 | |
| 1913 | target-module@13000 { /* 0x48313000, ap 97 62.0 */ |
| 1914 | compatible = "ti,sysc"; |
| 1915 | status = "disabled"; |
| 1916 | #address-cells = <1>; |
| 1917 | #size-cells = <1>; |
| 1918 | ranges = <0x0 0x13000 0x1000>; |
| 1919 | }; |
| 1920 | |
| 1921 | target-module@15000 { /* 0x48315000, ap 94 56.0 */ |
| 1922 | compatible = "ti,sysc"; |
| 1923 | status = "disabled"; |
| 1924 | #address-cells = <1>; |
| 1925 | #size-cells = <1>; |
| 1926 | ranges = <0x00000000 0x00015000 0x00001000>, |
| 1927 | <0x00001000 0x00016000 0x00001000>; |
| 1928 | }; |
| 1929 | |
| 1930 | target-module@18000 { /* 0x48318000, ap 74 4c.0 */ |
| 1931 | compatible = "ti,sysc"; |
| 1932 | status = "disabled"; |
| 1933 | #address-cells = <1>; |
| 1934 | #size-cells = <1>; |
| 1935 | ranges = <0x0 0x18000 0x4000>; |
| 1936 | }; |
| 1937 | |
| 1938 | target-module@20000 { /* 0x48320000, ap 99 34.0 */ |
| 1939 | compatible = "ti,sysc"; |
| 1940 | status = "disabled"; |
| 1941 | #address-cells = <1>; |
| 1942 | #size-cells = <1>; |
| 1943 | ranges = <0x0 0x20000 0x1000>; |
| 1944 | }; |
| 1945 | |
| 1946 | target-module@22000 { /* 0x48322000, ap 101 3e.0 */ |
| 1947 | compatible = "ti,sysc"; |
| 1948 | status = "disabled"; |
| 1949 | #address-cells = <1>; |
| 1950 | #size-cells = <1>; |
| 1951 | ranges = <0x0 0x22000 0x1000>; |
| 1952 | }; |
| 1953 | |
| 1954 | target-module@24000 { /* 0x48324000, ap 103 68.0 */ |
| 1955 | compatible = "ti,sysc"; |
| 1956 | status = "disabled"; |
| 1957 | #address-cells = <1>; |
| 1958 | #size-cells = <1>; |
| 1959 | ranges = <0x0 0x24000 0x1000>; |
| 1960 | }; |
| 1961 | }; |
| 1962 | }; |