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git01.mediatek.com / filogic / uboot / 4834e0405a0637c2713a480a65cae81896a531a4 / . / include / dm / uclass-id.h
blob: 33e43c20db66c019f1b7273258a8fd90a1b86494 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glassdd6ab882014-02-26 15:59:18 -0700[diff] [blame]2/*
3 * Copyright (c) 2013 Google, Inc
4 *
5 * (C) Copyright 2012
6 * Pavel Herrmann <morpheus.ibis@gmail.com>
Simon Glassdd6ab882014-02-26 15:59:18 -0700[diff] [blame]7 */
8
9#ifndef _DM_UCLASS_ID_H
10#define _DM_UCLASS_ID_H
11
12/* TODO(sjg@chromium.org): this could be compile-time generated */
13enum uclass_id {
14 /* These are used internally by driver model */
15 UCLASS_ROOT = 0,
16 UCLASS_DEMO,
17 UCLASS_TEST,
18 UCLASS_TEST_FDT,
Simon Glass791a17f2020-12-16 21:20:27 -0700[diff] [blame]19 UCLASS_TEST_FDT_MANUAL,
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]20 UCLASS_TEST_BUS,
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]21 UCLASS_TEST_PROBE,
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]22 UCLASS_TEST_DUMMY,
Simon Glass204675c2019-12-29 21:19:25 -0700[diff] [blame]23 UCLASS_TEST_DEVRES,
Simon Glass2d67fdf2020-04-08 16:57:34 -0600[diff] [blame]24 UCLASS_TEST_ACPI,
Simon Glass10a4a332014-10-13 23:41:53 -0600[diff] [blame]25 UCLASS_SPI_EMUL, /* sandbox SPI device emulator */
Simon Glassdaa54702014-12-10 08:55:49 -0700[diff] [blame]26 UCLASS_I2C_EMUL, /* sandbox I2C device emulator */
Simon Glass4b0ecc62018-11-18 08:14:33 -0700[diff] [blame]27 UCLASS_I2C_EMUL_PARENT, /* parent for I2C device emulators */
Simon Glassd9e90bb2015-03-05 12:25:28 -0700[diff] [blame]28 UCLASS_PCI_EMUL, /* sandbox PCI device emulator */
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]29 UCLASS_PCI_EMUL_PARENT, /* parent for PCI device emulators */
Simon Glass59d66d22015-03-25 12:22:37 -0600[diff] [blame]30 UCLASS_USB_EMUL, /* sandbox USB bus device emulator */
Mario Sixf95104d2018-08-09 14:51:18 +0200[diff] [blame]31 UCLASS_AXI_EMUL, /* sandbox AXI bus device emulator */
Simon Glassdd6ab882014-02-26 15:59:18 -0700[diff] [blame]32
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]33 /* U-Boot uclasses start here - in alphabetical order */
Simon Glass5e5c0cd2019-12-06 21:41:53 -0700[diff] [blame]34 UCLASS_ACPI_PMC, /* (x86) Power-management controller (PMC) */
Przemyslaw Marczake0cb85b2015-10-27 13:08:00 +0100[diff] [blame]35 UCLASS_ADC, /* Analog-to-digital converter */
Simon Glass85ee1652016-05-01 11:35:52 -0600[diff] [blame]36 UCLASS_AHCI, /* SATA disk controller */
Simon Glassed96cde2018-12-10 10:37:33 -0700[diff] [blame]37 UCLASS_AUDIO_CODEC, /* Audio codec with control and data path */
Philipp Tomsich872f4542018-11-25 19:38:54 +0100[diff] [blame]38 UCLASS_AXI, /* AXI bus */
Simon Glasscceee552016-02-29 15:25:55 -0700[diff] [blame]39 UCLASS_BLK, /* Block device */
Philipp Tomsichce860312018-11-27 23:00:18 +0100[diff] [blame]40 UCLASS_BOOTCOUNT, /* Bootcount backing store */
Simon Glass017656e2022-04-24 23:31:07 -0600[diff] [blame]41 UCLASS_BOOTDEV, /* Boot device for locating an OS to boot */
Simon Glass4b508b82022-04-24 23:31:08 -0600[diff] [blame]42 UCLASS_BOOTMETH, /* Bootmethod for booting an OS */
Simon Glass08ad13e2022-04-24 23:31:06 -0600[diff] [blame]43 UCLASS_BOOTSTD, /* Standard boot driver */
Philippe Reynes3483aa22020-07-24 18:19:45 +0200[diff] [blame]44 UCLASS_BUTTON, /* Button */
Dinh Nguyend94e18e2019-04-23 16:55:03 -0500[diff] [blame]45 UCLASS_CACHE, /* Cache controller */
Simon Glass36ad2342015-06-23 15:39:15 -0600[diff] [blame]46 UCLASS_CLK, /* Clock source, e.g. used by peripherals */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]47 UCLASS_CPU, /* CPU, typically part of an SoC */
48 UCLASS_CROS_EC, /* Chrome OS EC */
Simon Glass7d3d7762016-01-21 19:45:00 -0700[diff] [blame]49 UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
Mugunthan V N8c3c9182016-02-15 15:31:37 +0530[diff] [blame]50 UCLASS_DMA, /* Direct Memory Access */
Claudiu Manoilc0566c22021-01-25 14:23:53 +0200[diff] [blame]51 UCLASS_DSA, /* Distributed (Ethernet) Switch Architecture */
Simon Glass4834e042023-01-17 10:47:11 -0700[diff] [blame^]52 UCLASS_DSI_HOST, /* Display Serial Interface host */
Alexandru Gagniuc98198832021-07-29 11:47:15 -0500[diff] [blame]53 UCLASS_ECDSA, /* Elliptic curve cryptographic device */
Simon Glass15c4d672021-12-04 08:56:30 -0700[diff] [blame]54 UCLASS_EFI_LOADER, /* Devices created by UEFI applications */
Simon Glass507ab962021-12-04 08:56:31 -0700[diff] [blame]55 UCLASS_EFI_MEDIA, /* Devices provided by UEFI firmware */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]56 UCLASS_ETH, /* Ethernet device */
Ye Licd5bb772020-05-03 22:41:14 +0800[diff] [blame]57 UCLASS_ETH_PHY, /* Ethernet PHY device */
Philipp Tomsich872f4542018-11-25 19:38:54 +0100[diff] [blame]58 UCLASS_FIRMWARE, /* Firmware */
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200[diff] [blame]59 UCLASS_FPGA, /* FPGA device */
Andrew Sculld1d2c572022-05-30 10:00:08 +0000[diff] [blame]60 UCLASS_FUZZING_ENGINE, /* Fuzzing engine */
Tien Fong Chee5ca878b2018-07-06 16:28:03 +0800[diff] [blame]61 UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */
Sughosh Ganu0f9399a2022-10-21 18:15:55 +0530[diff] [blame]62 UCLASS_FWU_MDATA, /* FWU Metadata Access */
Simon Glasscebcebb2014-07-23 06:55:17 -0600[diff] [blame]63 UCLASS_GPIO, /* Bank of general-purpose I/O pins */
Chia-Wei Wang6e844742021-07-30 09:08:03 +0800[diff] [blame]64 UCLASS_HASH, /* Hash device */
Benjamin Gaignarda550b542018-11-27 13:49:50 +0100[diff] [blame]65 UCLASS_HWSPINLOCK, /* Hardware semaphores */
Simon Glass884c2f82022-10-29 19:47:15 -0600[diff] [blame]66 UCLASS_HOST, /* Sandbox host device */
Simon Glassc7a58902014-12-10 08:55:47 -0700[diff] [blame]67 UCLASS_I2C, /* I2C bus */
Simon Glass6ca4ba02014-12-10 08:55:54 -0700[diff] [blame]68 UCLASS_I2C_EEPROM, /* I2C EEPROM device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]69 UCLASS_I2C_GENERIC, /* Generic I2C device */
Simon Glass2a80c402015-08-03 08:19:21 -0600[diff] [blame]70 UCLASS_I2C_MUX, /* I2C multiplexer */
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]71 UCLASS_I2S, /* I2S bus */
Bin Mengb650afa2017-09-10 05:12:51 -0700[diff] [blame]72 UCLASS_IDE, /* IDE device */
Mark Kettenise1311b62021-10-23 16:58:01 +0200[diff] [blame]73 UCLASS_IOMMU, /* IOMMU */
Simon Glass18a8e092016-01-19 21:32:25 -0700[diff] [blame]74 UCLASS_IRQ, /* Interrupt controller */
Simon Glass02f0c282015-09-08 11:15:11 -0600[diff] [blame]75 UCLASS_KEYBOARD, /* Keyboard input device */
Simon Glasscce3aed2015-06-23 15:38:45 -0600[diff] [blame]76 UCLASS_LED, /* Light-emitting diode (LED) */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]77 UCLASS_LPC, /* x86 'low pin count' interface */
Stephen Warrend0107832016-05-13 15:50:29 -0600[diff] [blame]78 UCLASS_MAILBOX, /* Mailbox controller */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]79 UCLASS_MASS_STORAGE, /* Mass storage device */
Alex Marginean1a5b0982019-06-03 19:10:30 +0300[diff] [blame]80 UCLASS_MDIO, /* MDIO bus */
Alex Margineanab8c2a52019-07-12 10:13:50 +0300[diff] [blame]81 UCLASS_MDIO_MUX, /* MDIO MUX/switch */
Roger Quadrosb0679a72022-10-20 16:30:46 +0300[diff] [blame]82 UCLASS_MEMORY, /* Memory Controller device */
Thomas Choub1ed6862015-10-07 20:20:51 +0800[diff] [blame]83 UCLASS_MISC, /* Miscellaneous device */
Simon Glass1e8eb1b2015-06-23 15:38:48 -0600[diff] [blame]84 UCLASS_MMC, /* SD / MMC card or chip */
Ruchika Gupta98ebb122015-01-23 16:01:52 +0530[diff] [blame]85 UCLASS_MOD_EXP, /* RSA Mod Exp device */
Thomas Choue51b65e2015-11-07 14:20:31 +0800[diff] [blame]86 UCLASS_MTD, /* Memory Technology Device (MTD) device */
Jean-Jacques Hiblotf4f90562020-10-16 16:16:30 +0530[diff] [blame]87 UCLASS_MUX, /* Multiplexer device */
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200[diff] [blame]88 UCLASS_NOP, /* No-op devices */
Simon Glass29ce97e2016-01-17 16:11:14 -0700[diff] [blame]89 UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */
Zhikang Zhang182fccd2017-08-03 02:30:56 -0700[diff] [blame]90 UCLASS_NVME, /* NVM Express device */
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700[diff] [blame]91 UCLASS_P2SB, /* (x86) Primary-to-Sideband Bus */
Simon Glass14d1c8e2016-01-21 19:44:58 -0700[diff] [blame]92 UCLASS_PANEL, /* Display panel, such as an LCD */
Simon Glass8f790482016-01-21 19:44:56 -0700[diff] [blame]93 UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */
AKASHI Takahiroefb9a9d2022-04-19 10:05:09 +0900[diff] [blame]94 UCLASS_PARTITION, /* Logical disk partition device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]95 UCLASS_PCH, /* x86 platform controller hub */
Simon Glassb94dc892015-03-05 12:25:25 -0700[diff] [blame]96 UCLASS_PCI, /* PCI bus */
Ramon Fried663686d2019-04-27 11:15:21 +0300[diff] [blame]97 UCLASS_PCI_EP, /* PCI endpoint device */
Simon Glassb94dc892015-03-05 12:25:25 -0700[diff] [blame]98 UCLASS_PCI_GENERIC, /* Generic PCI bus device */
Jean-Jacques Hiblot48447782017-04-24 11:51:27 +0200[diff] [blame]99 UCLASS_PHY, /* Physical Layer (PHY) device */
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900[diff] [blame]100 UCLASS_PINCONFIG, /* Pin configuration node device */
Bin Meng1cc7ecd2016-06-22 02:29:47 -0700[diff] [blame]101 UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */
Simon Glass682ae862015-05-22 15:42:14 -0600[diff] [blame]102 UCLASS_PMIC, /* PMIC I/O device */
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]103 UCLASS_POWER_DOMAIN, /* (SoC) Power domains */
Simon Glass4834e042023-01-17 10:47:11 -0700[diff] [blame^]104 UCLASS_PVBLOCK, /* Xen virtual block device */
Philipp Tomsich872f4542018-11-25 19:38:54 +0100[diff] [blame]105 UCLASS_PWM, /* Pulse-width modulator */
Simon Glassc9795172016-01-21 19:43:31 -0700[diff] [blame]106 UCLASS_PWRSEQ, /* Power sequence device */
Asherah Connor4ffa95d2021-03-19 18:21:40 +1100[diff] [blame]107 UCLASS_QFW, /* QEMU firmware config device */
Bin Meng1cc7ecd2016-06-22 02:29:47 -0700[diff] [blame]108 UCLASS_RAM, /* RAM controller */
Nandor Hanca6d5ad2021-06-10 16:56:43 +0300[diff] [blame]109 UCLASS_REBOOT_MODE, /* Reboot mode */
Simon Glass682ae862015-05-22 15:42:14 -0600[diff] [blame]110 UCLASS_REGULATOR, /* Regulator device */
Nishanth Menon08b9dc22015-09-17 15:42:39 -0500[diff] [blame]111 UCLASS_REMOTEPROC, /* Remote Processor device */
Stephen Warren185ad872016-06-17 09:43:58 -0600[diff] [blame]112 UCLASS_RESET, /* Reset controller device */
Sughosh Ganu90592ed2019-12-28 23:58:27 +0530[diff] [blame]113 UCLASS_RNG, /* Random Number Generator */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]114 UCLASS_RTC, /* Real time clock device */
Etienne Carriere02fd1262020-09-09 18:44:00 +0200[diff] [blame]115 UCLASS_SCMI_AGENT, /* Interface with an SCMI server */
Michal Simekc886f352016-09-08 15:06:45 +0200[diff] [blame]116 UCLASS_SCSI, /* SCSI device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]117 UCLASS_SERIAL, /* Serial UART */
Simon Glass78df8b42018-11-18 08:14:32 -0700[diff] [blame]118 UCLASS_SIMPLE_BUS, /* Bus with child devices */
Ramon Friedcf1e49f2018-07-02 02:57:55 +0300[diff] [blame]119 UCLASS_SMEM, /* Shared memory interface */
Dave Gerlach50a6c082020-07-15 23:39:57 -0500[diff] [blame]120 UCLASS_SOC, /* SOC Device */
Simon Glass76072ac2018-12-10 10:37:36 -0700[diff] [blame]121 UCLASS_SOUND, /* Playing simple sounds */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]122 UCLASS_SPI, /* SPI bus */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]123 UCLASS_SPI_FLASH, /* SPI flash */
Simon Glass682ae862015-05-22 15:42:14 -0600[diff] [blame]124 UCLASS_SPI_GENERIC, /* Generic SPI flash target */
Philipp Tomsich872f4542018-11-25 19:38:54 +0100[diff] [blame]125 UCLASS_SPMI, /* System Power Management Interface bus */
Simon Glass6a84aaf2015-06-23 15:38:43 -0600[diff] [blame]126 UCLASS_SYSCON, /* System configuration device */
Simon Glass458b66a2020-11-05 06:32:05 -0700[diff] [blame]127 UCLASS_SYSINFO, /* Device information from hardware */
Stephen Warren859f2562016-05-12 12:03:35 -0600[diff] [blame]128 UCLASS_SYSRESET, /* System reset device */
Jens Wiklander14290442018-09-25 16:40:09 +0200[diff] [blame]129 UCLASS_TEE, /* Trusted Execution Environment device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]130 UCLASS_THERMAL, /* Thermal sensor */
Thomas Choufb798b12015-10-09 13:46:34 +0800[diff] [blame]131 UCLASS_TIMER, /* Timer device */
Simon Glass6c7a2322015-08-22 18:31:31 -0600[diff] [blame]132 UCLASS_TPM, /* Trusted Platform Module TIS interface */
Faiz Abbas5cc51072019-10-15 18:24:36 +0530[diff] [blame]133 UCLASS_UFS, /* Universal Flash Storage */
Simon Glass9b82eeb2015-03-25 12:21:59 -0600[diff] [blame]134 UCLASS_USB, /* USB bus */
Simon Glassc79173e2015-03-25 12:22:31 -0600[diff] [blame]135 UCLASS_USB_DEV_GENERIC, /* USB generic device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]136 UCLASS_USB_HUB, /* USB hub */
Jean-Jacques Hiblot9dc0d5c2018-11-29 10:52:46 +0100[diff] [blame]137 UCLASS_USB_GADGET_GENERIC, /* USB generic device */
Simon Glass623d28f2016-01-18 19:52:15 -0700[diff] [blame]138 UCLASS_VIDEO, /* Video or LCD device */
Simon Glass7cf17572015-07-02 18:16:08 -0600[diff] [blame]139 UCLASS_VIDEO_BRIDGE, /* Video bridge, e.g. DisplayPort to LVDS */
Simon Glass84c7fb32016-01-18 19:52:17 -0700[diff] [blame]140 UCLASS_VIDEO_CONSOLE, /* Text console driver for video device */
Mario Six1b773202018-09-27 09:19:29 +0200[diff] [blame]141 UCLASS_VIDEO_OSD, /* On-screen display */
Bin Mengdb7ca2e2018-10-15 02:21:00 -0700[diff] [blame]142 UCLASS_VIRTIO, /* VirtIO transport device */
Maxime Ripardbdbdca32018-09-18 10:35:24 +0300[diff] [blame]143 UCLASS_W1, /* Dallas 1-Wire bus */
Maxime Ripardf674fc02018-09-18 10:35:27 +0300[diff] [blame]144 UCLASS_W1_EEPROM, /* one-wire EEPROMs */
Chris Packhamf5c98112019-02-18 08:48:04 +1300[diff] [blame]145 UCLASS_WDT, /* Watchdog Timer driver */
Simon Glassdd6ab882014-02-26 15:59:18 -0700[diff] [blame]146
Simon Glassdd6ab882014-02-26 15:59:18 -0700[diff] [blame]147 UCLASS_COUNT,
148 UCLASS_INVALID = -1,
149};
150
151#endif