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Tim Schendekehl024b61c2011-11-01 23:55:01 +00001/*
2 * (C) Copyright 2011
3 * egnite GmbH <info@egnite.de>
4 *
5 * Configuation settings for Ethernut 5 with AT91SAM9XE.
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Tim Schendekehl024b61c2011-11-01 23:55:01 +00008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include <asm/hardware.h>
14
15/* The first stage boot loader expects u-boot running at this address. */
16#define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */
17
18/* The first stage boot loader takes care of low level initialization. */
19#define CONFIG_SKIP_LOWLEVEL_INIT
20
21/* Set our official architecture number. */
22#define MACH_TYPE_ETHERNUT5 1971
23#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
24
25/* CPU information */
Tim Schendekehl024b61c2011-11-01 23:55:01 +000026#define CONFIG_ARCH_CPU_INIT
27
28/* ARM asynchronous clock */
29#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
30#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Tim Schendekehl024b61c2011-11-01 23:55:01 +000031
32/* 32kB internal SRAM */
33#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
34#define CONFIG_SRAM_SIZE (32 << 10)
Rob Herring72e6d652012-07-13 09:44:01 +000035#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
36 GENERATED_GBL_DATA_SIZE)
Tim Schendekehl024b61c2011-11-01 23:55:01 +000037
38/* 128MB SDRAM in 1 bank */
39#define CONFIG_NR_DRAM_BANKS 1
40#define CONFIG_SYS_SDRAM_BASE 0x20000000
41#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
42#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
43#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
44#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
45#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
46#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
47 - CONFIG_SYS_MALLOC_LEN)
48
49/* 512kB on-chip NOR flash */
50# define CONFIG_SYS_MAX_FLASH_BANKS 1
51# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
52# define CONFIG_AT91_EFLASH
53# define CONFIG_SYS_MAX_FLASH_SECT 32
54# define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */
55# define CONFIG_EFLASH_PROTSECTORS 1
56
57/* 512kB DataFlash at NPCS0 */
58#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
59#define CONFIG_HAS_DATAFLASH
Tim Schendekehl024b61c2011-11-01 23:55:01 +000060#define CONFIG_ATMEL_DATAFLASH_SPI
61#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
62#define DATAFLASH_TCSS (0x1a << 16)
63#define DATAFLASH_TCHS (0x1 << 24)
64
65#define CONFIG_ENV_IS_IN_SPI_FLASH
66#define CONFIG_ENV_OFFSET 0x3DE000
67#define CONFIG_ENV_SECT_SIZE (132 << 10)
68#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
69#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
70 + CONFIG_ENV_OFFSET)
71#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
72 + 0x042000)
73
74/* SPI */
75#define CONFIG_ATMEL_SPI
Tim Schendekehl024b61c2011-11-01 23:55:01 +000076#define AT91_SPI_CLK 15000000
77
78/* Serial port */
79#define CONFIG_ATMEL_USART
80#define CONFIG_USART3 /* USART 3 is DBGU */
81#define CONFIG_BAUDRATE 115200
Tim Schendekehl024b61c2011-11-01 23:55:01 +000082#define CONFIG_USART_BASE ATMEL_BASE_DBGU
83#define CONFIG_USART_ID ATMEL_ID_SYS
84
85/* Misc. hardware drivers */
86#define CONFIG_AT91_GPIO
87
88/* Command line configuration */
Tim Schendekehl024b61c2011-11-01 23:55:01 +000089#define CONFIG_CMD_JFFS2
Tim Schendekehl024b61c2011-11-01 23:55:01 +000090#define CONFIG_CMD_MTDPARTS
91#define CONFIG_CMD_NAND
Tim Schendekehl024b61c2011-11-01 23:55:01 +000092
Joe Hershberger5a9d7f12015-06-22 16:15:30 -050093#ifndef MINIMAL_LOADER
Tim Schendekehl024b61c2011-11-01 23:55:01 +000094#define CONFIG_CMD_BSP
Tim Schendekehl024b61c2011-11-01 23:55:01 +000095#define CONFIG_CMD_DATE
Tim Schendekehl024b61c2011-11-01 23:55:01 +000096#define CONFIG_CMD_REISER
97#define CONFIG_CMD_SAVES
Tim Schendekehl024b61c2011-11-01 23:55:01 +000098#define CONFIG_CMD_UBIFS
99#define CONFIG_CMD_UNZIP
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000100#endif
101
102/* NAND flash */
103#ifdef CONFIG_CMD_NAND
104#define CONFIG_SYS_MAX_NAND_DEVICE 1
105#define CONFIG_SYS_NAND_BASE 0x40000000
106#define CONFIG_SYS_NAND_DBW_8
107#define CONFIG_NAND_ATMEL
108/* our ALE is AD21 */
109#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
110/* our CLE is AD22 */
111#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmanna4c24d32013-11-29 12:13:45 +0100112#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000113#endif
114
115/* JFFS2 */
116#ifdef CONFIG_CMD_JFFS2
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000117#define CONFIG_JFFS2_CMDLINE
118#define CONFIG_JFFS2_NAND
119#endif
120
121/* Ethernet */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000122#define CONFIG_NET_RETRY_COUNT 20
123#define CONFIG_MACB
124#define CONFIG_RMII
125#define CONFIG_PHY_ID 0
126#define CONFIG_MACB_SEARCH_PHY
127
128/* MMC */
129#ifdef CONFIG_CMD_MMC
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000130#define CONFIG_GENERIC_MMC
131#define CONFIG_GENERIC_ATMEL_MCI
132#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
133#endif
134
135/* USB */
136#ifdef CONFIG_CMD_USB
137#define CONFIG_USB_ATMEL
Bo Shen4a985df2013-10-21 16:14:00 +0800138#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000139#define CONFIG_USB_OHCI_NEW
140#define CONFIG_SYS_USB_OHCI_CPU_INIT
141#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
142#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
143#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000144#endif
145
146/* RTC */
147#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
148#define CONFIG_RTC_PCF8563
149#define CONFIG_SYS_I2C_RTC_ADDR 0x51
150#endif
151
152/* I2C */
153#define CONFIG_SYS_MAX_I2C_BUS 1
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100154
155#define CONFIG_SYS_I2C
156#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
157#define CONFIG_SYS_I2C_SOFT_SPEED 100000
158#define CONFIG_SYS_I2C_SOFT_SLAVE 0
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000159
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000160#define I2C_SOFT_DECLARATIONS
161
162#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
163#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
164
165#define I2C_INIT { \
166 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
167 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
168 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
169 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
170 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
171}
172
173#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
174#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
175#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
176#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
177#define I2C_DELAY udelay(100)
178#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
179
180/* DHCP/BOOTP options */
181#ifdef CONFIG_CMD_DHCP
182#define CONFIG_BOOTP_BOOTFILESIZE
183#define CONFIG_BOOTP_BOOTPATH
184#define CONFIG_BOOTP_GATEWAY
185#define CONFIG_BOOTP_HOSTNAME
186#define CONFIG_SYS_AUTOLOAD "n"
187#endif
188
189/* File systems */
190#define CONFIG_MTD_DEVICE
191#define CONFIG_MTD_PARTITIONS
192#if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
193#define MTDIDS_DEFAULT "nand0=atmel_nand"
194#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)"
195#endif
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000196#define CONFIG_LZO
197#define CONFIG_RBTREE
198
199/* Boot command */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000200#define CONFIG_CMDLINE_TAG
201#define CONFIG_SETUP_MEMORY_TAGS
202#define CONFIG_INITRD_TAG
203#define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
204#if defined(CONFIG_CMD_NAND)
205#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
206 "root=/dev/mtdblock0 " \
207 MTDPARTS_DEFAULT \
208 " rw rootfstype=jffs2"
209#endif
210
211/* Misc. u-boot settings */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000212#define CONFIG_SYS_CBSIZE 256
213#define CONFIG_SYS_MAXARGS 16
214#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \
215 + sizeof(CONFIG_SYS_PROMPT))
216#define CONFIG_SYS_LONGHELP
217#define CONFIG_CMDLINE_EDITING
218
219#endif