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Daniel Hellstroma2d96db2008-03-26 23:26:48 +01001/* Configuration header file for Gaisler GR-XC3S-1500
2 * spartan board.
3 *
4 * (C) Copyright 2003-2005
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2007
8 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Daniel Hellstroma2d96db2008-03-26 23:26:48 +010011 */
12
13#ifndef __CONFIG_H__
14#define __CONFIG_H__
15
16/*
17 * High Level Configuration Options
18 * (easy to change)
19 */
20
21#define CONFIG_LEON3 /* This is an LEON3 CPU */
22#define CONFIG_LEON 1 /* This is an LEON CPU */
23#define CONFIG_GRXC3S1500 1 /* ... on GR-XC3S-1500 board */
24
25/* CPU / AMBA BUS configuration */
Wolfgang Denka1be4762008-05-20 16:00:29 +020026#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */
Daniel Hellstroma2d96db2008-03-26 23:26:48 +010027
28/* Number of SPARC register windows */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020029#define CONFIG_SYS_SPARC_NWINDOWS 8
Daniel Hellstroma2d96db2008-03-26 23:26:48 +010030
31/*
32 * Serial console configuration
33 */
34#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020035#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Daniel Hellstroma2d96db2008-03-26 23:26:48 +010036
37/* Partitions */
38#define CONFIG_DOS_PARTITION
39#define CONFIG_MAC_PARTITION
40#define CONFIG_ISO_PARTITION
41
42/*
43 * Supported commands
44 */
45#include <config_cmd_default.h>
46
47#define CONFIG_CMD_REGINFO
48#define CONFIG_CMD_AMBAPP
49#define CONFIG_CMD_PING
50#define CONFIG_CMD_DIAG
51#define CONFIG_CMD_IRQ
52
53/*
54 * Autobooting
55 */
56#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
57
58#define CONFIG_PREBOOT "echo;" \
59 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
60 "echo"
61
62#undef CONFIG_BOOTARGS
63
64#define CONFIG_EXTRA_ENV_SETTINGS \
65 "netdev=eth0\0" \
66 "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
67 "nfsroot=${serverip}:${rootpath}\0" \
68 "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
69 "addip=setenv bootargs ${bootargs} " \
70 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
71 ":${hostname}:${netdev}:off panic=1\0" \
72 "flash_nfs=run nfsargs addip;" \
73 "bootm ${kernel_addr}\0" \
74 "flash_self=run ramargs addip;" \
75 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
76 "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
77 "scratch=40200000\0" \
Mike Frysingerc3c6bf12011-10-12 19:47:51 +000078 "getkernel=tftpboot $(scratch) $(bootfile)\0" \
Daniel Hellstroma2d96db2008-03-26 23:26:48 +010079 "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.206:192.168.0.20:192.168.0.1:255.255.255.0:grxc3s1500_daniel:eth0\0" \
80 ""
81
82#define CONFIG_NETMASK 255.255.255.0
83#define CONFIG_GATEWAYIP 192.168.0.1
84#define CONFIG_SERVERIP 192.168.0.20
85#define CONFIG_IPADDR 192.168.0.206
Joe Hershberger257ff782011-10-13 13:03:47 +000086#define CONFIG_ROOTPATH "/export/rootfs"
Daniel Hellstroma2d96db2008-03-26 23:26:48 +010087#define CONFIG_HOSTNAME grxc3s1500
Joe Hershbergere4da2482011-10-13 13:03:48 +000088#define CONFIG_BOOTFILE "/uImage"
Daniel Hellstroma2d96db2008-03-26 23:26:48 +010089
90#define CONFIG_BOOTCOMMAND "run flash_self"
91
92/* Memory MAP
93 *
94 * Flash:
95 * |--------------------------------|
96 * | 0x00000000 Text & Data & BSS | *
97 * | for Monitor | *
98 * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
99 * | UNUSED / Growth | * 256kb
100 * |--------------------------------|
101 * | 0x00050000 Base custom area | *
102 * | kernel / FS | *
103 * | | * Rest of Flash
104 * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
105 * | END-0x00008000 Environment | * 32kb
106 * |--------------------------------|
107 *
108 *
109 *
110 * Main Memory:
111 * |--------------------------------|
112 * | UNUSED / scratch area |
113 * | |
114 * | |
115 * | |
116 * | |
117 * |--------------------------------|
118 * | Monitor .Text / .DATA / .BSS | * 256kb
119 * | Relocated! | *
120 * |--------------------------------|
121 * | Monitor Malloc | * 128kb (contains relocated environment)
122 * |--------------------------------|
123 * | Monitor/kernel STACK | * 64kb
124 * |--------------------------------|
125 * | Page Table for MMU systems | * 2k
126 * |--------------------------------|
127 * | PROM Code accessed from Linux | * 6kb-128b
128 * |--------------------------------|
129 * | Global data (avail from kernel)| * 128b
130 * |--------------------------------|
131 *
132 */
133
134/*
135 * Flash configuration (8,16 or 32 MB)
136 * TEXT base always at 0xFFF00000
137 * ENV_ADDR always at 0xFFF40000
138 * FLASH_BASE at 0xFC000000 for 64 MB
139 * 0xFE000000 for 32 MB
140 * 0xFF000000 for 16 MB
141 * 0xFF800000 for 8 MB
142 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143/*#define CONFIG_SYS_NO_FLASH 1*/
144#define CONFIG_SYS_FLASH_BASE 0x00000000
145#define CONFIG_SYS_FLASH_SIZE 0x00800000
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100146
147#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
149#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100150
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
152#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
153#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
154#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
155#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100156
157/*** CFI CONFIG ***/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200159#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200160#define CONFIG_SYS_FLASH_CFI
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100161/* Bypass cache when reading regs from flash memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200162#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100163/* Buffered writes (32byte/go) instead of single accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100165
166/*
167 * Environment settings
168 */
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200169/*#define CONFIG_ENV_IS_NOWHERE 1*/
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200170#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200171/* CONFIG_ENV_ADDR need to be at sector boundary */
172#define CONFIG_ENV_SIZE 0x8000
173#define CONFIG_ENV_SECT_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200174#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100175#define CONFIG_ENV_OVERWRITE 1
176
177/*
178 * Memory map
179 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180#define CONFIG_SYS_SDRAM_BASE 0x40000000
181#define CONFIG_SYS_SDRAM_SIZE 0x4000000
182#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100183
184/* no SRAM available */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#undef CONFIG_SYS_SRAM_BASE
186#undef CONFIG_SYS_SRAM_SIZE
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100187
188/* Always Run U-Boot from SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200189#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
190#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
191#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100192
Wolfgang Denk0191e472010-10-26 14:34:52 +0200193#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100194
Wolfgang Denk0191e472010-10-26 14:34:52 +0200195#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100197
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
199#define CONFIG_SYS_STACK_SIZE (0x10000-32)
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100200
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200201#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
203# define CONFIG_SYS_RAMBOOT 1
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100204#endif
205
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
207#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
208#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100209
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
211#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100212
213/* relocated monitor area */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
215#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100216
217/* make un relocated address from relocated address */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200218#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100219
220/*
221 * Ethernet configuration
222 */
223#define CONFIG_GRETH 1
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100224
225/* Default GRETH Ethernet HARDWARE address */
226#define GRETH_HWADDR_0 0x00
227#define GRETH_HWADDR_1 0x00
228#define GRETH_HWADDR_2 0x7a
229#define GRETH_HWADDR_3 0xcc
230#define GRETH_HWADDR_4 0x00
231#define GRETH_HWADDR_5 0x12
232
233#define CONFIG_ETHADDR 00:00:7a:cc:00:12
234#define CONFIG_PHY_ADDR 0x00
235
236/*
237 * Miscellaneous configurable options
238 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200239#define CONFIG_SYS_LONGHELP /* undef to save memory */
240#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100241#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200242#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100243#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200244#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100245#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200246#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
247#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
248#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100249
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200250#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
251#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100252
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200253#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100254
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200255#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100256
257/*
258 * Various low-level settings
259 */
260
261/*-----------------------------------------------------------------------
262 * USB stuff
263 *-----------------------------------------------------------------------
264 */
265#define CONFIG_USB_CLOCK 0x0001BBBB
266#define CONFIG_USB_CONFIG 0x00005000
267
268/***** Gaisler GRLIB IP-Cores Config ********/
269
270/* AMBA Plug & Play info display on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200271/*#define CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP*/
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100272
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200273#define CONFIG_SYS_GRLIB_SDRAM 0
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100274
275/* See, GRLIB Docs (grip.pdf) on how to set up
276 * These the memory controller registers.
277 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200278#define CONFIG_SYS_GRLIB_MEMCFG1 (0x000000ff | (1<<11))
279#define CONFIG_SYS_GRLIB_MEMCFG2 0x82206000
280#define CONFIG_SYS_GRLIB_MEMCFG3 0x00136000
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100281
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200282#define CONFIG_SYS_GRLIB_FT_MEMCFG1 (0x000000ff | (1<<11))
283#define CONFIG_SYS_GRLIB_FT_MEMCFG2 0x82206000
284#define CONFIG_SYS_GRLIB_FT_MEMCFG3 0x00136000
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100285
286/* no DDR controller */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200287#define CONFIG_SYS_GRLIB_DDR_CFG 0x00000000
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100288
289/* no DDR2 Controller */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200290#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
291#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100292
293/* Calculate scaler register value from default baudrate */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200294#define CONFIG_SYS_GRLIB_APBUART_SCALER \
Daniel Hellstroma2d96db2008-03-26 23:26:48 +0100295 ((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
296
297/* Identification string */
298#define CONFIG_IDENT_STRING "GAISLER LEON3 GR-XC3S-1500"
299
300/* default kernel command line */
301#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
302
303#endif /* __CONFIG_H */