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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada52f0c512016-03-18 16:41:52 +09002/*
3 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada52f0c512016-03-18 16:41:52 +09004 */
5
6#include <common.h>
7#include <debug_uart.h>
8#include <linux/io.h>
9#include <linux/serial_reg.h>
10
Masahiro Yamada3cac7f72019-06-29 02:38:06 +090011#include "../sg-regs.h"
Masahiro Yamada52f0c512016-03-18 16:41:52 +090012#include "../soc-info.h"
13#include "debug-uart.h"
14
15#define UNIPHIER_UART_TX 0x00
16#define UNIPHIER_UART_LCR_MCR 0x10
17#define UNIPHIER_UART_LSR 0x14
18#define UNIPHIER_UART_LDR 0x24
19
20static void _debug_uart_putc(int c)
21{
22 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
23
24 while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE))
25 ;
26
27 writel(c, base + UNIPHIER_UART_TX);
28}
29
Masahiro Yamada3cac7f72019-06-29 02:38:06 +090030#ifdef CONFIG_SPL_BUILD
31void sg_set_pinsel(unsigned int pin, unsigned int muxval,
32 unsigned int mux_bits, unsigned int reg_stride)
33{
34 unsigned int shift = pin * mux_bits % 32;
Masahiro Yamada76b31242019-07-10 20:07:40 +090035 void __iomem *reg = sg_base + SG_PINCTRL_BASE +
36 pin * mux_bits / 32 * reg_stride;
Masahiro Yamada3cac7f72019-06-29 02:38:06 +090037 u32 mask = (1U << mux_bits) - 1;
38 u32 tmp;
39
40 tmp = readl(reg);
41 tmp &= ~(mask << shift);
42 tmp |= (mask & muxval) << shift;
43 writel(tmp, reg);
44}
45
46void sg_set_iectrl(unsigned int pin)
47{
48 unsigned int bit = pin % 32;
Masahiro Yamada76b31242019-07-10 20:07:40 +090049 void __iomem *reg = sg_base + SG_IECTRL + pin / 32 * 4;
Masahiro Yamada3cac7f72019-06-29 02:38:06 +090050 u32 tmp;
51
52 tmp = readl(reg);
53 tmp |= 1 << bit;
54 writel(tmp, reg);
55}
56#endif
57
Masahiro Yamada52f0c512016-03-18 16:41:52 +090058void _debug_uart_init(void)
59{
Masahiro Yamada1950f122019-06-29 02:38:05 +090060#ifdef CONFIG_SPL_BUILD
Masahiro Yamada52f0c512016-03-18 16:41:52 +090061 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
62 unsigned int divisor;
63
Masahiro Yamada31649052017-01-21 18:05:26 +090064 switch (uniphier_get_soc_id()) {
Masahiro Yamada52f0c512016-03-18 16:41:52 +090065#if defined(CONFIG_ARCH_UNIPHIER_LD4)
Masahiro Yamada31649052017-01-21 18:05:26 +090066 case UNIPHIER_LD4_ID:
Masahiro Yamada52f0c512016-03-18 16:41:52 +090067 divisor = uniphier_ld4_debug_uart_init();
68 break;
69#endif
70#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
Masahiro Yamada31649052017-01-21 18:05:26 +090071 case UNIPHIER_PRO4_ID:
Masahiro Yamada52f0c512016-03-18 16:41:52 +090072 divisor = uniphier_pro4_debug_uart_init();
73 break;
74#endif
75#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
Masahiro Yamada31649052017-01-21 18:05:26 +090076 case UNIPHIER_SLD8_ID:
Masahiro Yamada52f0c512016-03-18 16:41:52 +090077 divisor = uniphier_sld8_debug_uart_init();
78 break;
79#endif
80#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
Masahiro Yamada31649052017-01-21 18:05:26 +090081 case UNIPHIER_PRO5_ID:
Masahiro Yamada52f0c512016-03-18 16:41:52 +090082 divisor = uniphier_pro5_debug_uart_init();
83 break;
84#endif
85#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
Masahiro Yamada31649052017-01-21 18:05:26 +090086 case UNIPHIER_PXS2_ID:
Masahiro Yamada52f0c512016-03-18 16:41:52 +090087 divisor = uniphier_pxs2_debug_uart_init();
88 break;
89#endif
90#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
Masahiro Yamada31649052017-01-21 18:05:26 +090091 case UNIPHIER_LD6B_ID:
Masahiro Yamada52f0c512016-03-18 16:41:52 +090092 divisor = uniphier_ld6b_debug_uart_init();
93 break;
94#endif
Masahiro Yamada52f0c512016-03-18 16:41:52 +090095 default:
96 return;
97 }
98
99 writel(UART_LCR_WLEN8 << 8, base + UNIPHIER_UART_LCR_MCR);
100
101 writel(divisor, base + UNIPHIER_UART_LDR);
Masahiro Yamada1950f122019-06-29 02:38:05 +0900102#endif
Masahiro Yamada52f0c512016-03-18 16:41:52 +0900103}
104DEBUG_UART_FUNCS