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git01.mediatek.com / filogic / uboot / 4808fbc9f79deab7934b3eb2518a8a39870e11d5 / . / arch / arm / dts / stm32mp15-pinctrl.dtsi
blob: 8d00391978ae8d1726a1ac8c27856f802cd238a1 [file] [log] [blame]
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8&pinctrl {
9 adc1_in6_pins_a: adc1-in6 {
10 pins {
11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
12 };
13 };
14
15 adc12_ain_pins_a: adc12-ain-0 {
16 pins {
17 pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
18 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
19 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
20 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
21 };
22 };
23
24 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
25 pins {
26 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
27 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
28 };
29 };
30
31 cec_pins_a: cec-0 {
32 pins {
33 pinmux = <STM32_PINMUX('A', 15, AF4)>;
34 bias-disable;
35 drive-open-drain;
36 slew-rate = <0>;
37 };
38 };
39
40 cec_pins_sleep_a: cec-sleep-0 {
41 pins {
42 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
43 };
44 };
45
46 cec_pins_b: cec-1 {
47 pins {
48 pinmux = <STM32_PINMUX('B', 6, AF5)>;
49 bias-disable;
50 drive-open-drain;
51 slew-rate = <0>;
52 };
53 };
54
55 cec_pins_sleep_b: cec-sleep-1 {
56 pins {
57 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
58 };
59 };
60
61 dac_ch1_pins_a: dac-ch1 {
62 pins {
63 pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
64 };
65 };
66
67 dac_ch2_pins_a: dac-ch2 {
68 pins {
69 pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
70 };
71 };
72
73 dcmi_pins_a: dcmi-0 {
74 pins {
75 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
76 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
77 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
78 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
79 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
80 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
81 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
82 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
83 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
84 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
85 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
86 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
87 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
88 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
89 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
90 bias-disable;
91 };
92 };
93
94 dcmi_sleep_pins_a: dcmi-sleep-0 {
95 pins {
96 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
97 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
98 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
99 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
100 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
101 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
102 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
103 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
104 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
105 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
106 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
107 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
108 <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
109 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
110 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
111 };
112 };
113
114 ethernet0_rgmii_pins_a: rgmii-0 {
115 pins1 {
116 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
117 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
118 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
119 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
120 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
121 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
122 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
123 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
124 bias-disable;
125 drive-push-pull;
126 slew-rate = <2>;
127 };
128 pins2 {
129 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
130 bias-disable;
131 drive-push-pull;
132 slew-rate = <0>;
133 };
134 pins3 {
135 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
136 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
137 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
138 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
139 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
140 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
141 bias-disable;
142 };
143 };
144
145 ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
146 pins1 {
147 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
148 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
149 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
150 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
151 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
152 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
153 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
154 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
155 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
156 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
157 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
158 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
159 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
160 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
161 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
162 };
163 };
164
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]165 ethernet0_rgmii_pins_b: rgmii-1 {
166 pins1 {
167 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
168 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
169 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
170 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
171 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
172 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
173 <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */
174 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
175 bias-disable;
176 drive-push-pull;
177 slew-rate = <2>;
178 };
179 pins2 {
180 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
181 bias-disable;
182 drive-push-pull;
183 slew-rate = <0>;
184 };
185 pins3 {
186 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
187 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
188 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
189 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
190 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
191 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
192 bias-disable;
193 };
194 };
195
196 ethernet0_rgmii_pins_sleep_b: rgmii-sleep-1 {
197 pins1 {
198 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
199 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
200 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
201 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
202 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
203 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
204 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
205 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
206 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
207 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
208 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
209 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
210 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
211 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
212 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
213 };
214 };
215
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]216 ethernet0_rmii_pins_a: rmii-0 {
217 pins1 {
218 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
219 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
220 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
221 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
222 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
223 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
224 bias-disable;
225 drive-push-pull;
226 slew-rate = <2>;
227 };
228 pins2 {
229 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
230 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
231 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
232 bias-disable;
233 };
234 };
235
236 ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
237 pins1 {
238 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
239 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
240 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
241 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
242 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
243 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
244 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
245 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
246 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
247 };
248 };
249
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]250 fmc_pins_a: fmc-0 {
251 pins1 {
252 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
253 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
254 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
255 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
256 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
257 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
258 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
259 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
260 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
261 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
262 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
263 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
264 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
265 bias-disable;
266 drive-push-pull;
267 slew-rate = <1>;
268 };
269 pins2 {
270 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
271 bias-pull-up;
272 };
273 };
274
275 fmc_sleep_pins_a: fmc-sleep-0 {
276 pins {
277 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
278 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
279 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
280 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
281 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
282 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
283 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
284 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
285 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
286 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
287 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
288 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
289 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
290 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
291 };
292 };
293
294 i2c1_pins_a: i2c1-0 {
295 pins {
296 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
297 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
298 bias-disable;
299 drive-open-drain;
300 slew-rate = <0>;
301 };
302 };
303
304 i2c1_pins_sleep_a: i2c1-1 {
305 pins {
306 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
307 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
308 };
309 };
310
311 i2c1_pins_b: i2c1-2 {
312 pins {
313 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
314 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
315 bias-disable;
316 drive-open-drain;
317 slew-rate = <0>;
318 };
319 };
320
321 i2c1_pins_sleep_b: i2c1-3 {
322 pins {
323 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
324 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
325 };
326 };
327
328 i2c2_pins_a: i2c2-0 {
329 pins {
330 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
331 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
332 bias-disable;
333 drive-open-drain;
334 slew-rate = <0>;
335 };
336 };
337
338 i2c2_pins_sleep_a: i2c2-1 {
339 pins {
340 pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
341 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
342 };
343 };
344
345 i2c2_pins_b1: i2c2-2 {
346 pins {
347 pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
348 bias-disable;
349 drive-open-drain;
350 slew-rate = <0>;
351 };
352 };
353
354 i2c2_pins_sleep_b1: i2c2-3 {
355 pins {
356 pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
357 };
358 };
359
360 i2c5_pins_a: i2c5-0 {
361 pins {
362 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
363 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
364 bias-disable;
365 drive-open-drain;
366 slew-rate = <0>;
367 };
368 };
369
370 i2c5_pins_sleep_a: i2c5-1 {
371 pins {
372 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
373 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
374
375 };
376 };
377
378 i2s2_pins_a: i2s2-0 {
379 pins {
380 pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
381 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
382 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
383 slew-rate = <1>;
384 drive-push-pull;
385 bias-disable;
386 };
387 };
388
389 i2s2_pins_sleep_a: i2s2-1 {
390 pins {
391 pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
392 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
393 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
394 };
395 };
396
397 ltdc_pins_a: ltdc-a-0 {
398 pins {
399 pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
400 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
401 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
402 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
403 <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
404 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
405 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
406 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
407 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
408 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
409 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
410 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
411 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
412 <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
413 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
414 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
415 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
416 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
417 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
418 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
419 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
420 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
421 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
422 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
423 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
424 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
425 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
426 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
427 bias-disable;
428 drive-push-pull;
429 slew-rate = <1>;
430 };
431 };
432
433 ltdc_pins_sleep_a: ltdc-a-1 {
434 pins {
435 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
436 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
437 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
438 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
439 <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
440 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
441 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
442 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
443 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
444 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
445 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
446 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
447 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
448 <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
449 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
450 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
451 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
452 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
453 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
454 <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
455 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
456 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
457 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
458 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
459 <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
460 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
461 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
462 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
463 };
464 };
465
466 ltdc_pins_b: ltdc-b-0 {
467 pins {
468 pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
469 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
470 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
471 <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
472 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
473 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
474 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
475 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
476 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
477 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
478 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
479 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
480 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
481 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
482 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
483 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
484 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
485 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
486 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
487 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
488 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
489 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
490 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
491 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
492 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
493 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
494 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
495 <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
496 bias-disable;
497 drive-push-pull;
498 slew-rate = <1>;
499 };
500 };
501
502 ltdc_pins_sleep_b: ltdc-b-1 {
503 pins {
504 pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
505 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
506 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
507 <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
508 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
509 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
510 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
511 <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
512 <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
513 <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
514 <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
515 <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
516 <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
517 <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
518 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
519 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
520 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
521 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
522 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
523 <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
524 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
525 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
526 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
527 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
528 <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
529 <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
530 <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
531 <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
532 };
533 };
534
535 m_can1_pins_a: m-can1-0 {
536 pins1 {
537 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
538 slew-rate = <1>;
539 drive-push-pull;
540 bias-disable;
541 };
542 pins2 {
543 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
544 bias-disable;
545 };
546 };
547
548 m_can1_sleep_pins_a: m_can1-sleep-0 {
549 pins {
550 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
551 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
552 };
553 };
554
555 pwm1_pins_a: pwm1-0 {
556 pins {
557 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
558 <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
559 <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
560 bias-pull-down;
561 drive-push-pull;
562 slew-rate = <0>;
563 };
564 };
565
566 pwm1_sleep_pins_a: pwm1-sleep-0 {
567 pins {
568 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
569 <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
570 <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
571 };
572 };
573
574 pwm2_pins_a: pwm2-0 {
575 pins {
576 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
577 bias-pull-down;
578 drive-push-pull;
579 slew-rate = <0>;
580 };
581 };
582
583 pwm2_sleep_pins_a: pwm2-sleep-0 {
584 pins {
585 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
586 };
587 };
588
589 pwm3_pins_a: pwm3-0 {
590 pins {
591 pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
592 bias-pull-down;
593 drive-push-pull;
594 slew-rate = <0>;
595 };
596 };
597
598 pwm3_sleep_pins_a: pwm3-sleep-0 {
599 pins {
600 pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
601 };
602 };
603
604 pwm4_pins_a: pwm4-0 {
605 pins {
606 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
607 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
608 bias-pull-down;
609 drive-push-pull;
610 slew-rate = <0>;
611 };
612 };
613
614 pwm4_sleep_pins_a: pwm4-sleep-0 {
615 pins {
616 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
617 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
618 };
619 };
620
621 pwm4_pins_b: pwm4-1 {
622 pins {
623 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
624 bias-pull-down;
625 drive-push-pull;
626 slew-rate = <0>;
627 };
628 };
629
630 pwm4_sleep_pins_b: pwm4-sleep-1 {
631 pins {
632 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
633 };
634 };
635
636 pwm5_pins_a: pwm5-0 {
637 pins {
638 pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */
639 bias-pull-down;
640 drive-push-pull;
641 slew-rate = <0>;
642 };
643 };
644
645 pwm5_sleep_pins_a: pwm5-sleep-0 {
646 pins {
647 pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */
648 };
649 };
650
651 pwm8_pins_a: pwm8-0 {
652 pins {
653 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
654 bias-pull-down;
655 drive-push-pull;
656 slew-rate = <0>;
657 };
658 };
659
660 pwm8_sleep_pins_a: pwm8-sleep-0 {
661 pins {
662 pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
663 };
664 };
665
666 pwm12_pins_a: pwm12-0 {
667 pins {
668 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
669 bias-pull-down;
670 drive-push-pull;
671 slew-rate = <0>;
672 };
673 };
674
675 pwm12_sleep_pins_a: pwm12-sleep-0 {
676 pins {
677 pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */
678 };
679 };
680
681 qspi_clk_pins_a: qspi-clk-0 {
682 pins {
683 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
684 bias-disable;
685 drive-push-pull;
686 slew-rate = <3>;
687 };
688 };
689
690 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
691 pins {
692 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
693 };
694 };
695
696 qspi_bk1_pins_a: qspi-bk1-0 {
697 pins1 {
698 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
699 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
700 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
701 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
702 bias-disable;
703 drive-push-pull;
704 slew-rate = <1>;
705 };
706 pins2 {
707 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
708 bias-pull-up;
709 drive-push-pull;
710 slew-rate = <1>;
711 };
712 };
713
714 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
715 pins {
716 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
717 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
718 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
719 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
720 <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
721 };
722 };
723
724 qspi_bk2_pins_a: qspi-bk2-0 {
725 pins1 {
726 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
727 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
728 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
729 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
730 bias-disable;
731 drive-push-pull;
732 slew-rate = <1>;
733 };
734 pins2 {
735 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
736 bias-pull-up;
737 drive-push-pull;
738 slew-rate = <1>;
739 };
740 };
741
742 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
743 pins {
744 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
745 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
746 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
747 <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
748 <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
749 };
750 };
751
752 sai2a_pins_a: sai2a-0 {
753 pins {
754 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
755 <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
756 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
757 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
758 slew-rate = <0>;
759 drive-push-pull;
760 bias-disable;
761 };
762 };
763
764 sai2a_sleep_pins_a: sai2a-1 {
765 pins {
766 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
767 <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
768 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
769 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
770 };
771 };
772
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]773 sai2a_pins_b: sai2a-2 {
774 pins1 {
775 pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
776 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
777 <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */
778 slew-rate = <0>;
779 drive-push-pull;
780 bias-disable;
781 };
782 };
783
784 sai2a_sleep_pins_b: sai2a-sleep-3 {
785 pins {
786 pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
787 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
788 <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */
789 };
790 };
791
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]792 sai2b_pins_a: sai2b-0 {
793 pins1 {
794 pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
795 <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
796 <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
797 slew-rate = <0>;
798 drive-push-pull;
799 bias-disable;
800 };
801 pins2 {
802 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
803 bias-disable;
804 };
805 };
806
807 sai2b_sleep_pins_a: sai2b-1 {
808 pins {
809 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
810 <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
811 <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
812 <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
813 };
814 };
815
816 sai2b_pins_b: sai2b-2 {
817 pins {
818 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
819 bias-disable;
820 };
821 };
822
823 sai2b_sleep_pins_b: sai2b-3 {
824 pins {
825 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
826 };
827 };
828
829 sai4a_pins_a: sai4a-0 {
830 pins {
831 pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
832 slew-rate = <0>;
833 drive-push-pull;
834 bias-disable;
835 };
836 };
837
838 sai4a_sleep_pins_a: sai4a-1 {
839 pins {
840 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
841 };
842 };
843
844 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
845 pins1 {
846 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
847 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
848 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
849 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
850 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
851 slew-rate = <1>;
852 drive-push-pull;
853 bias-disable;
854 };
855 pins2 {
856 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
857 slew-rate = <2>;
858 drive-push-pull;
859 bias-disable;
860 };
861 };
862
863 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
864 pins1 {
865 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
866 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
867 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
868 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
869 slew-rate = <1>;
870 drive-push-pull;
871 bias-disable;
872 };
873 pins2 {
874 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
875 slew-rate = <2>;
876 drive-push-pull;
877 bias-disable;
878 };
879 pins3 {
880 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
881 slew-rate = <1>;
882 drive-open-drain;
883 bias-disable;
884 };
885 };
886
887 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
888 pins {
889 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
890 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
891 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
892 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
893 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
894 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
895 };
896 };
897
898 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
899 pins1 {
900 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
901 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
902 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
903 slew-rate = <1>;
904 drive-push-pull;
905 bias-pull-up;
906 };
907 pins2{
908 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
909 bias-pull-up;
910 };
911 };
912
913 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
914 pins {
915 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
916 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
917 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
918 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
919 };
920 };
921
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]922 sdmmc1_dir_pins_b: sdmmc1-dir-1 {
923 pins1 {
924 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
925 <STM32_PINMUX('E', 14, AF8)>, /* SDMMC1_D123DIR */
926 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
927 slew-rate = <1>;
928 drive-push-pull;
929 bias-pull-up;
930 };
931 pins2{
932 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
933 bias-pull-up;
934 };
935 };
936
937 sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
938 pins {
939 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
940 <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */
941 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
942 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
943 };
944 };
945
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]946 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
947 pins1 {
948 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
949 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
950 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
951 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
952 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
953 slew-rate = <1>;
954 drive-push-pull;
955 bias-pull-up;
956 };
957 pins2 {
958 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
959 slew-rate = <2>;
960 drive-push-pull;
961 bias-pull-up;
962 };
963 };
964
965 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
966 pins1 {
967 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
968 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
969 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
970 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
971 slew-rate = <1>;
972 drive-push-pull;
973 bias-pull-up;
974 };
975 pins2 {
976 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
977 slew-rate = <2>;
978 drive-push-pull;
979 bias-pull-up;
980 };
981 pins3 {
982 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
983 slew-rate = <1>;
984 drive-open-drain;
985 bias-pull-up;
986 };
987 };
988
989 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
990 pins {
991 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
992 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
993 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
994 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
995 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
996 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
997 };
998 };
999
1000 sdmmc2_b4_pins_b: sdmmc2-b4-1 {
1001 pins1 {
1002 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
1003 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
1004 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
1005 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
1006 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
1007 slew-rate = <1>;
1008 drive-push-pull;
1009 bias-disable;
1010 };
1011 pins2 {
1012 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
1013 slew-rate = <2>;
1014 drive-push-pull;
1015 bias-disable;
1016 };
1017 };
1018
1019 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
1020 pins1 {
1021 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
1022 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
1023 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
1024 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
1025 slew-rate = <1>;
1026 drive-push-pull;
1027 bias-disable;
1028 };
1029 pins2 {
1030 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
1031 slew-rate = <2>;
1032 drive-push-pull;
1033 bias-disable;
1034 };
1035 pins3 {
1036 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
1037 slew-rate = <1>;
1038 drive-open-drain;
1039 bias-disable;
1040 };
1041 };
1042
1043 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
1044 pins {
1045 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1046 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1047 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
1048 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
1049 slew-rate = <1>;
1050 drive-push-pull;
1051 bias-pull-up;
1052 };
1053 };
1054
1055 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
1056 pins {
1057 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1058 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1059 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
1060 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
1061 };
1062 };
1063
Patrick Delaunay8aee15d2020-04-21 12:27:35 +0200[diff] [blame]1064 sdmmc2_d47_pins_b: sdmmc2-d47-1 {
1065 pins {
1066 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1067 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
1068 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
1069 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
1070 slew-rate = <1>;
1071 drive-push-pull;
1072 bias-pull-up;
1073 };
1074 };
1075
1076 sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
1077 pins {
1078 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1079 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
1080 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
1081 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
1082 };
1083 };
1084
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1085 sdmmc3_b4_pins_a: sdmmc3-b4-0 {
1086 pins1 {
1087 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1088 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1089 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
1090 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
1091 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
1092 slew-rate = <1>;
1093 drive-push-pull;
1094 bias-pull-up;
1095 };
1096 pins2 {
1097 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
1098 slew-rate = <2>;
1099 drive-push-pull;
1100 bias-pull-up;
1101 };
1102 };
1103
1104 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
1105 pins1 {
1106 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1107 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1108 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
1109 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
1110 slew-rate = <1>;
1111 drive-push-pull;
1112 bias-pull-up;
1113 };
1114 pins2 {
1115 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
1116 slew-rate = <2>;
1117 drive-push-pull;
1118 bias-pull-up;
1119 };
1120 pins3 {
1121 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
1122 slew-rate = <1>;
1123 drive-open-drain;
1124 bias-pull-up;
1125 };
1126 };
1127
1128 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
1129 pins {
1130 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
1131 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
1132 <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
1133 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
1134 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
1135 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
1136 };
1137 };
1138
1139 spdifrx_pins_a: spdifrx-0 {
1140 pins {
1141 pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
1142 bias-disable;
1143 };
1144 };
1145
1146 spdifrx_sleep_pins_a: spdifrx-1 {
1147 pins {
1148 pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
1149 };
1150 };
1151
1152 spi2_pins_a: spi2-0 {
1153 pins1 {
1154 pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
1155 <STM32_PINMUX('I', 0, AF5)>, /* SPI2_NSS */
1156 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
1157 bias-disable;
1158 drive-push-pull;
1159 slew-rate = <3>;
1160 };
1161 pins2 {
1162 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
1163 bias-disable;
1164 };
1165 };
1166
1167 stusb1600_pins_a: stusb1600-0 {
1168 pins {
1169 pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
1170 bias-pull-up;
1171 };
1172 };
1173
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]1174 usart3_pins_a: usart3-0 {
1175 pins1 {
1176 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
1177 bias-disable;
1178 drive-push-pull;
1179 slew-rate = <0>;
1180 };
1181 pins2 {
1182 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
1183 bias-disable;
1184 };
1185 };
1186
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1187 uart4_pins_a: uart4-0 {
1188 pins1 {
1189 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
1190 bias-disable;
1191 drive-push-pull;
1192 slew-rate = <0>;
1193 };
1194 pins2 {
1195 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
1196 bias-disable;
1197 };
1198 };
1199
1200 uart4_pins_b: uart4-1 {
1201 pins1 {
1202 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
1203 bias-disable;
1204 drive-push-pull;
1205 slew-rate = <0>;
1206 };
1207 pins2 {
1208 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
1209 bias-disable;
1210 };
1211 };
1212
1213 uart7_pins_a: uart7-0 {
1214 pins1 {
1215 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
1216 bias-disable;
1217 drive-push-pull;
1218 slew-rate = <0>;
1219 };
1220 pins2 {
1221 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
1222 <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
1223 <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
1224 bias-disable;
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200[diff] [blame]1225 };
1226 };
1227
1228 uart8_pins_a: uart8-0 {
1229 pins1 {
1230 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
1231 bias-disable;
1232 drive-push-pull;
1233 slew-rate = <0>;
1234 };
1235 pins2 {
1236 pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
1237 bias-disable;
1238 };
1239 };
1240
1241 usbotg_hs_pins_a: usbotg-hs-0 {
1242 pins {
1243 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
1244 };
1245 };
1246
1247 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
1248 pins {
1249 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
1250 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]1251 };
1252 };
1253};
1254
1255&pinctrl_z {
1256 i2c2_pins_b2: i2c2-0 {
1257 pins {
1258 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
1259 bias-disable;
1260 drive-open-drain;
1261 slew-rate = <0>;
1262 };
1263 };
1264
1265 i2c2_pins_sleep_b2: i2c2-1 {
1266 pins {
1267 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
1268 };
1269 };
1270
1271 i2c4_pins_a: i2c4-0 {
1272 pins {
1273 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
1274 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
1275 bias-disable;
1276 drive-open-drain;
1277 slew-rate = <0>;
1278 };
1279 };
1280
1281 i2c4_pins_sleep_a: i2c4-1 {
1282 pins {
1283 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
1284 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
1285 };
1286 };
1287
1288 spi1_pins_a: spi1-0 {
1289 pins1 {
1290 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
1291 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
1292 bias-disable;
1293 drive-push-pull;
1294 slew-rate = <1>;
1295 };
1296
1297 pins2 {
1298 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
1299 bias-disable;
1300 };
1301 };
1302};