| developer | b3c8f17 | 2019-12-31 11:29:19 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2019 MediaTek Inc. |
| 4 | * Author: Mingming Lee <mingming.lee@mediatek.com> |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #include <dt-bindings/clock/mt8512-clk.h> |
| 9 | #include <dt-bindings/gpio/gpio.h> |
| 10 | #include <dt-bindings/interrupt-controller/irq.h> |
| 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 12 | |
| 13 | / { |
| 14 | compatible = "mediatek,mt8512"; |
| 15 | interrupt-parent = <&sysirq>; |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; |
| 18 | |
| 19 | gic: interrupt-controller@c000000 { |
| 20 | compatible = "arm,gic-v3"; |
| 21 | #interrupt-cells = <3>; |
| 22 | interrupt-parent = <&gic>; |
| 23 | interrupt-controller; |
| 24 | reg = <0xc000000 0x40000>, /* GICD */ |
| 25 | <0xc080000 0x200000>; /* GICR */ |
| 26 | interrupts = <GIC_PPI 9 |
| 27 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| 28 | }; |
| 29 | |
| 30 | topckgen: clock-controller@10000000 { |
| 31 | compatible = "mediatek,mt8512-topckgen"; |
| 32 | reg = <0x10000000 0x1000>; |
| 33 | #clock-cells = <1>; |
| 34 | }; |
| 35 | |
| 36 | topckgen_cg: clock-controller-cg@10000000 { |
| 37 | compatible = "mediatek,mt8512-topckgen-cg"; |
| 38 | reg = <0x10000000 0x1000>; |
| 39 | #clock-cells = <1>; |
| 40 | }; |
| 41 | |
| 42 | infracfg: clock-controller@10001000 { |
| 43 | compatible = "mediatek,mt8512-infracfg"; |
| 44 | reg = <0x10001000 0x1000>; |
| 45 | #clock-cells = <1>; |
| 46 | }; |
| 47 | |
| 48 | pinctrl: pinctrl@10005000 { |
| 49 | compatible = "mediatek,mt8512-pinctrl"; |
| 50 | reg = <0x10005000 0x1000>; |
| 51 | gpio: gpio-controller { |
| 52 | gpio-controller; |
| 53 | #gpio-cells = <2>; |
| 54 | }; |
| 55 | }; |
| 56 | |
| 57 | watchdog0: watchdog@10007000 { |
| 58 | compatible = "mediatek,wdt"; |
| 59 | reg = <0x10007000 0x1000>; |
| 60 | interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>; |
| 61 | #reset-cells = <1>; |
| 62 | status = "disabled"; |
| 63 | timeout-sec = <60>; |
| 64 | reset-on-timeout; |
| 65 | }; |
| 66 | |
| 67 | timer0: apxgpt@10008000 { |
| 68 | compatible = "mediatek,timer"; |
| 69 | reg = <0x10008000 0x1000>; |
| 70 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>; |
| 71 | clocks = <&topckgen CLK_TOP_SYS_26M_D2>, |
| 72 | <&topckgen CLK_TOP_CLK32K>, |
| 73 | <&infracfg CLK_INFRA_APXGPT>; |
| 74 | clock-names = "clk13m", |
| 75 | "clk32k", |
| 76 | "bus"; |
| 77 | }; |
| 78 | |
| 79 | apmixedsys: clock-controller@1000c000 { |
| 80 | compatible = "mediatek,mt8512-apmixedsys"; |
| 81 | reg = <0x1000c000 0x1000>; |
| 82 | #clock-cells = <1>; |
| 83 | }; |
| 84 | |
| 85 | sysirq: interrupt-controller@10200a80 { |
| 86 | compatible = "mediatek,sysirq"; |
| 87 | interrupt-controller; |
| 88 | #interrupt-cells = <3>; |
| 89 | interrupt-parent = <&gic>; |
| 90 | reg = <0x10200a80 0x50>; |
| 91 | }; |
| 92 | |
| 93 | uart0: serial@11002000 { |
| 94 | compatible = "mediatek,hsuart"; |
| 95 | reg = <0x11002000 0x1000>; |
| 96 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; |
| 97 | clocks = <&topckgen CLK_TOP_CLK26M>, |
| 98 | <&infracfg CLK_INFRA_UART0>; |
| 99 | clock-names = "baud", "bus"; |
| 100 | status = "disabled"; |
| 101 | }; |
| 102 | |
| 103 | mmc0: mmc@11230000 { |
| 104 | compatible = "mediatek,mt8512-mmc"; |
| 105 | reg = <0x11230000 0x1000>, |
| 106 | <0x11cd0000 0x1000>; |
| 107 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; |
| 108 | clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, |
| 109 | <&infracfg CLK_INFRA_MSDC0>, |
| 110 | <&infracfg CLK_INFRA_MSDC0_SRC>; |
| 111 | clock-names = "source", "hclk", "source_cg"; |
| 112 | status = "disabled"; |
| 113 | }; |
| 114 | |
| 115 | }; |