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git01.mediatek.com / filogic / uboot / 47f7e5fca63f76b01b934fe679a259b8c7e4212b / . / arch / arm / dts / k3-am62a7-r5-sk.dts
blob: bc05dcb5efbe1844d52ebd05e2cce8cf3f69c624 [file] [log] [blame]
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AM62A7 SK dts file for R5 SPL
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
7#include "k3-am62a7-sk.dts"
8#include "k3-am62a-ddr-1866mhz-32bit.dtsi"
9#include "k3-am62a-ddr.dtsi"
10
11#include "k3-am62a7-sk-u-boot.dtsi"
12
13/ {
14 aliases {
15 remoteproc0 = &sysctrler;
16 remoteproc1 = &a53_0;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]17 };
18
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]19 a53_0: a53@0 {
20 compatible = "ti,am654-rproc";
21 reg = <0x00 0x00a90000 0x00 0x10>;
22 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
Manorit Chawdhry5c760a62023-04-14 09:47:58 +0530[diff] [blame]23 <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
24 <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]25 resets = <&k3_reset 135 0>;
26 clocks = <&k3_clks 61 0>;
27 assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
28 assigned-clock-parents = <&k3_clks 61 2>;
29 assigned-clock-rates = <200000000>, <1200000000>;
30 ti,sci = <&dmsc>;
31 ti,sci-proc-id = <32>;
32 ti,sci-host-id = <10>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]34 };
35
36 dm_tifs: dm-tifs {
37 compatible = "ti,j721e-dm-sci";
38 ti,host-id = <36>;
39 ti,secure-host;
40 mbox-names = "rx", "tx";
41 mboxes= <&secure_proxy_main 22>,
42 <&secure_proxy_main 23>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]44 };
45};
46
47&dmsc {
48 mboxes= <&secure_proxy_main 0>,
49 <&secure_proxy_main 1>,
50 <&secure_proxy_main 0>;
51 mbox-names = "rx", "tx", "notify";
52 ti,host-id = <35>;
53 ti,secure-host;
54};
55
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]56&secure_proxy_sa3 {
57 /* Needed for initial handshake with ROM */
58 status = "okay";
59 bootph-pre-ram;
60};
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]61
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]62&cbass_main {
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]63 sysctrler: sysctrler {
64 compatible = "ti,am654-system-controller";
65 mboxes= <&secure_proxy_main 1>,
66 <&secure_proxy_main 0>,
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]67 <&secure_proxy_sa3 0>;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]68 mbox-names = "tx", "rx", "boot_notify";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]70 };
71};
72
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]73&wkup_uart0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]75};
76
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]77&main_uart1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]79};
80
81/* WKUP UART0 is used for DM firmware logs */
82&wkup_uart0 {
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]83 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]85};
86
87/* Main UART1 is used for TIFS firmware logs */
88&main_uart1 {
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]89 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]91};