| Wadim Egorov | abea324 | 2023-12-20 10:18:10 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * phyCORE-AM62x dts file for SPLs |
| 4 | * Copyright (C) 2022 - 2023 Phytec Messtechnik GmbH |
| 5 | * Author: Wadim Egorov <w.egorov@phytec.de> |
| 6 | * |
| 7 | * Product homepage: |
| 8 | * https://www.phytec.com/product/phyboard-am62x |
| 9 | */ |
| 10 | |
| 11 | #include "k3-am625-phycore-som-binman.dtsi" |
| 12 | |
| 13 | / { |
| 14 | chosen { |
| 15 | stdout-path = "serial2:115200n8"; |
| 16 | tick-timer = &main_timer0; |
| 17 | }; |
| 18 | |
| 19 | aliases { |
| 20 | mmc0 = &sdhci0; |
| 21 | mmc1 = &sdhci1; |
| 22 | }; |
| 23 | |
| 24 | memory@80000000 { |
| 25 | bootph-all; |
| 26 | }; |
| 27 | }; |
| 28 | |
| 29 | &cpsw3g { |
| 30 | bootph-all; |
| 31 | }; |
| 32 | |
| 33 | &cpsw_port1 { |
| 34 | bootph-all; |
| 35 | }; |
| 36 | |
| 37 | &cpsw_port2 { |
| 38 | status = "disabled"; |
| 39 | }; |
| 40 | |
| 41 | &cpsw3g_phy1 { |
| 42 | bootph-all; |
| 43 | }; |
| 44 | |
| Wadim Egorov | abea324 | 2023-12-20 10:18:10 +0100 | [diff] [blame] | 45 | &fss { |
| 46 | bootph-all; |
| 47 | }; |
| 48 | |
| 49 | &main_bcdma { |
| 50 | bootph-all; |
| 51 | reg = <0x00 0x485c0100 0x00 0x100>, |
| 52 | <0x00 0x4c000000 0x00 0x20000>, |
| 53 | <0x00 0x4a820000 0x00 0x20000>, |
| 54 | <0x00 0x4aa40000 0x00 0x20000>, |
| 55 | <0x00 0x4bc00000 0x00 0x100000>, |
| 56 | <0x00 0x48600000 0x00 0x8000>, |
| 57 | <0x00 0x484a4000 0x00 0x2000>, |
| 58 | <0x00 0x484c2000 0x00 0x2000>; |
| 59 | reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", |
| 60 | "ringrt" , "cfg", "tchan", "rchan"; |
| 61 | }; |
| 62 | |
| 63 | &main_gpio0 { |
| 64 | bootph-all; |
| 65 | }; |
| 66 | |
| 67 | &main_mdio1_pins_default { |
| 68 | bootph-all; |
| 69 | }; |
| 70 | |
| 71 | &main_i2c0 { |
| 72 | bootph-all; |
| 73 | }; |
| 74 | |
| 75 | &main_i2c0_pins_default { |
| 76 | bootph-all; |
| 77 | }; |
| 78 | |
| 79 | &main_mmc0_pins_default { |
| 80 | bootph-all; |
| 81 | }; |
| 82 | |
| 83 | &main_mmc1_pins_default { |
| 84 | bootph-all; |
| 85 | }; |
| 86 | |
| 87 | &main_pktdma { |
| 88 | bootph-all; |
| 89 | reg = <0x00 0x485c0000 0x00 0x100>, |
| 90 | <0x00 0x4a800000 0x00 0x20000>, |
| 91 | <0x00 0x4aa00000 0x00 0x20000>, |
| 92 | <0x00 0x4b800000 0x00 0x200000>, |
| 93 | <0x00 0x485e0000 0x00 0x10000>, |
| 94 | <0x00 0x484a0000 0x00 0x2000>, |
| 95 | <0x00 0x484c0000 0x00 0x2000>, |
| 96 | <0x00 0x48430000 0x00 0x1000>; |
| 97 | reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", |
| 98 | "cfg", "tchan", "rchan", "rflow"; |
| 99 | }; |
| 100 | |
| 101 | &main_rgmii1_pins_default { |
| 102 | bootph-all; |
| 103 | }; |
| 104 | |
| 105 | &main_timer0 { |
| 106 | clock-frequency = <25000000>; |
| 107 | }; |
| 108 | |
| 109 | &main_uart0 { |
| 110 | bootph-all; |
| 111 | }; |
| 112 | |
| 113 | &main_uart0_pins_default { |
| 114 | bootph-all; |
| 115 | }; |
| 116 | |
| 117 | &main_uart1 { |
| 118 | bootph-all; |
| 119 | }; |
| 120 | |
| 121 | &main_uart1_pins_default { |
| 122 | bootph-all; |
| 123 | }; |
| 124 | |
| 125 | &ospi0 { |
| 126 | bootph-all; |
| 127 | |
| 128 | flash@0 { |
| 129 | bootph-all; |
| 130 | }; |
| 131 | }; |
| 132 | |
| 133 | &ospi0_pins_default { |
| 134 | bootph-all; |
| 135 | }; |
| 136 | |
| 137 | &sdhci0 { |
| 138 | bootph-all; |
| 139 | }; |
| 140 | |
| 141 | &sdhci1 { |
| 142 | bootph-all; |
| 143 | }; |
| 144 | |
| 145 | &vcc_3v3_mmc { |
| 146 | bootph-all; |
| 147 | }; |
| 148 | |
| 149 | &vcc_5v0_som { |
| 150 | bootph-all; |
| 151 | }; |
| 152 | |
| 153 | &vddshv5_sdio { |
| 154 | bootph-all; |
| 155 | }; |
| 156 | |
| 157 | &wkup_uart0 { |
| 158 | bootph-all; |
| 159 | }; |