Chris Packham | 06db9d2 | 2018-12-10 20:07:51 +1300 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Device Tree Include file for Marvell Armada 385 SoC. |
| 4 | * |
| 5 | * Copyright (C) 2014 Marvell |
| 6 | * |
| 7 | * Lior Amsalem <alior@marvell.com> |
| 8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> |
| 9 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include "armada-38x.dtsi" |
| 13 | |
| 14 | / { |
| 15 | model = "Marvell Armada 385 family SoC"; |
| 16 | compatible = "marvell,armada385", "marvell,armada380"; |
| 17 | |
| 18 | cpus { |
| 19 | #address-cells = <1>; |
| 20 | #size-cells = <0>; |
| 21 | enable-method = "marvell,armada-380-smp"; |
| 22 | |
| 23 | cpu@0 { |
| 24 | device_type = "cpu"; |
| 25 | compatible = "arm,cortex-a9"; |
| 26 | reg = <0>; |
| 27 | }; |
| 28 | cpu@1 { |
| 29 | device_type = "cpu"; |
| 30 | compatible = "arm,cortex-a9"; |
| 31 | reg = <1>; |
| 32 | }; |
| 33 | }; |
| 34 | |
| 35 | soc { |
Chris Packham | 06db9d2 | 2018-12-10 20:07:51 +1300 | [diff] [blame] | 36 | pciec: pcie { |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 37 | compatible = "marvell,armada-370-pcie"; |
| 38 | status = "disabled"; |
| 39 | device_type = "pci"; |
| 40 | |
| 41 | #address-cells = <3>; |
| 42 | #size-cells = <2>; |
| 43 | |
| 44 | msi-parent = <&mpic>; |
| 45 | bus-range = <0x00 0xff>; |
| 46 | |
| 47 | ranges = |
| 48 | <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 |
| 49 | 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 |
| 50 | 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 |
| 51 | 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 |
| 52 | 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ |
| 53 | 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ |
| 54 | 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ |
| 55 | 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ |
| 56 | 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ |
| 57 | 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ |
| 58 | 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ |
| 59 | 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; |
| 60 | |
| 61 | /* |
| 62 | * This port can be either x4 or x1. When |
| 63 | * configured in x4 by the bootloader, then |
| 64 | * pcie@4,0 is not available. |
| 65 | */ |
Chris Packham | 06db9d2 | 2018-12-10 20:07:51 +1300 | [diff] [blame] | 66 | pcie1: pcie@1,0 { |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 67 | device_type = "pci"; |
| 68 | assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; |
| 69 | reg = <0x0800 0 0 0 0>; |
| 70 | #address-cells = <3>; |
| 71 | #size-cells = <2>; |
| 72 | #interrupt-cells = <1>; |
| 73 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 |
| 74 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; |
Chris Packham | 06db9d2 | 2018-12-10 20:07:51 +1300 | [diff] [blame] | 75 | bus-range = <0x00 0xff>; |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 76 | interrupt-map-mask = <0 0 0 0>; |
| 77 | interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| 78 | marvell,pcie-port = <0>; |
| 79 | marvell,pcie-lane = <0>; |
| 80 | clocks = <&gateclk 8>; |
Pali Rohár | 5fc93e2 | 2021-12-21 12:20:19 +0100 | [diff] [blame] | 81 | resets = <&systemc 0 0>; |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 82 | status = "disabled"; |
| 83 | }; |
| 84 | |
| 85 | /* x1 port */ |
Chris Packham | 06db9d2 | 2018-12-10 20:07:51 +1300 | [diff] [blame] | 86 | pcie2: pcie@2,0 { |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 87 | device_type = "pci"; |
| 88 | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; |
| 89 | reg = <0x1000 0 0 0 0>; |
| 90 | #address-cells = <3>; |
| 91 | #size-cells = <2>; |
| 92 | #interrupt-cells = <1>; |
| 93 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 |
| 94 | 0x81000000 0 0 0x81000000 0x2 0 1 0>; |
Chris Packham | 06db9d2 | 2018-12-10 20:07:51 +1300 | [diff] [blame] | 95 | bus-range = <0x00 0xff>; |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 96 | interrupt-map-mask = <0 0 0 0>; |
| 97 | interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| 98 | marvell,pcie-port = <1>; |
| 99 | marvell,pcie-lane = <0>; |
| 100 | clocks = <&gateclk 5>; |
Pali Rohár | 5fc93e2 | 2021-12-21 12:20:19 +0100 | [diff] [blame] | 101 | resets = <&systemc 0 1>; |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 102 | status = "disabled"; |
| 103 | }; |
| 104 | |
| 105 | /* x1 port */ |
Chris Packham | 06db9d2 | 2018-12-10 20:07:51 +1300 | [diff] [blame] | 106 | pcie3: pcie@3,0 { |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 107 | device_type = "pci"; |
| 108 | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; |
| 109 | reg = <0x1800 0 0 0 0>; |
| 110 | #address-cells = <3>; |
| 111 | #size-cells = <2>; |
| 112 | #interrupt-cells = <1>; |
| 113 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 |
| 114 | 0x81000000 0 0 0x81000000 0x3 0 1 0>; |
Chris Packham | 06db9d2 | 2018-12-10 20:07:51 +1300 | [diff] [blame] | 115 | bus-range = <0x00 0xff>; |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 116 | interrupt-map-mask = <0 0 0 0>; |
| 117 | interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
| 118 | marvell,pcie-port = <2>; |
| 119 | marvell,pcie-lane = <0>; |
| 120 | clocks = <&gateclk 6>; |
Pali Rohár | 5fc93e2 | 2021-12-21 12:20:19 +0100 | [diff] [blame] | 121 | resets = <&systemc 0 2>; |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 122 | status = "disabled"; |
| 123 | }; |
| 124 | |
| 125 | /* |
| 126 | * x1 port only available when pcie@1,0 is |
| 127 | * configured as a x1 port |
| 128 | */ |
Chris Packham | 06db9d2 | 2018-12-10 20:07:51 +1300 | [diff] [blame] | 129 | pcie4: pcie@4,0 { |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 130 | device_type = "pci"; |
| 131 | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; |
| 132 | reg = <0x2000 0 0 0 0>; |
| 133 | #address-cells = <3>; |
| 134 | #size-cells = <2>; |
| 135 | #interrupt-cells = <1>; |
| 136 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 |
| 137 | 0x81000000 0 0 0x81000000 0x4 0 1 0>; |
Chris Packham | 06db9d2 | 2018-12-10 20:07:51 +1300 | [diff] [blame] | 138 | bus-range = <0x00 0xff>; |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 139 | interrupt-map-mask = <0 0 0 0>; |
| 140 | interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| 141 | marvell,pcie-port = <3>; |
| 142 | marvell,pcie-lane = <0>; |
| 143 | clocks = <&gateclk 7>; |
Pali Rohár | 5fc93e2 | 2021-12-21 12:20:19 +0100 | [diff] [blame] | 144 | resets = <&systemc 0 3>; |
Stefan Roese | ac5efba | 2015-08-31 07:33:57 +0200 | [diff] [blame] | 145 | status = "disabled"; |
| 146 | }; |
| 147 | }; |
| 148 | }; |
| 149 | }; |
Chris Packham | 06db9d2 | 2018-12-10 20:07:51 +1300 | [diff] [blame] | 150 | |
| 151 | &pinctrl { |
| 152 | compatible = "marvell,mv88f6820-pinctrl"; |
| 153 | }; |