| Ley Foon Tan | f80cb34 | 2018-05-24 00:17:24 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
| 4 | * |
| 5 | */ |
| 6 | |
| 7 | #include <altera.h> |
| 8 | #include <common.h> |
| 9 | #include <errno.h> |
| 10 | #include <fdtdec.h> |
| 11 | #include <miiphy.h> |
| 12 | #include <netdev.h> |
| 13 | #include <asm/io.h> |
| 14 | #include <asm/arch/reset_manager.h> |
| 15 | #include <asm/arch/system_manager.h> |
| 16 | #include <asm/arch/misc.h> |
| 17 | #include <asm/pl310.h> |
| 18 | #include <linux/libfdt.h> |
| 19 | |
| 20 | #include <dt-bindings/reset/altr,rst-mgr-s10.h> |
| 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
| 24 | static struct socfpga_system_manager *sysmgr_regs = |
| 25 | (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
| 26 | |
| 27 | /* |
| 28 | * DesignWare Ethernet initialization |
| 29 | */ |
| 30 | #ifdef CONFIG_ETH_DESIGNWARE |
| 31 | |
| 32 | static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode) |
| 33 | { |
| 34 | u32 modereg; |
| 35 | |
| 36 | if (!phymode) |
| 37 | return -EINVAL; |
| 38 | |
| 39 | if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) |
| 40 | modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; |
| 41 | else if (!strcmp(phymode, "rgmii")) |
| 42 | modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; |
| 43 | else if (!strcmp(phymode, "rmii")) |
| 44 | modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; |
| 45 | else |
| 46 | return -EINVAL; |
| 47 | |
| 48 | clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index, |
| 49 | SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, |
| 50 | modereg); |
| 51 | |
| 52 | return 0; |
| 53 | } |
| 54 | |
| 55 | static int socfpga_set_phymode(void) |
| 56 | { |
| 57 | const void *fdt = gd->fdt_blob; |
| 58 | struct fdtdec_phandle_args args; |
| 59 | const char *phy_mode; |
| 60 | u32 gmac_index; |
| 61 | int nodes[2]; /* Max. 3 GMACs */ |
| 62 | int ret, count; |
| 63 | int i, node; |
| 64 | |
| 65 | count = fdtdec_find_aliases_for_id(fdt, "ethernet", |
| 66 | COMPAT_ALTERA_SOCFPGA_DWMAC, |
| 67 | nodes, ARRAY_SIZE(nodes)); |
| 68 | for (i = 0; i < count; i++) { |
| 69 | node = nodes[i]; |
| 70 | if (node <= 0) |
| 71 | continue; |
| 72 | |
| 73 | ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", |
| 74 | "#reset-cells", 1, 0, |
| 75 | &args); |
| 76 | if (ret || args.args_count != 1) { |
| 77 | debug("GMAC%i: Failed to parse DT 'resets'!\n", i); |
| 78 | continue; |
| 79 | } |
| 80 | |
| 81 | gmac_index = args.args[0] - EMAC0_RESET; |
| 82 | |
| 83 | phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); |
| 84 | ret = socfpga_phymode_setup(gmac_index, phy_mode); |
| 85 | if (ret) { |
| 86 | debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); |
| 87 | continue; |
| 88 | } |
| 89 | } |
| 90 | |
| 91 | return 0; |
| 92 | } |
| 93 | #else |
| 94 | static int socfpga_set_phymode(void) |
| 95 | { |
| 96 | return 0; |
| 97 | }; |
| 98 | #endif |
| 99 | |
| 100 | /* |
| 101 | * Print CPU information |
| 102 | */ |
| 103 | #if defined(CONFIG_DISPLAY_CPUINFO) |
| 104 | int print_cpuinfo(void) |
| 105 | { |
| 106 | puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n"); |
| 107 | |
| 108 | return 0; |
| 109 | } |
| 110 | #endif |
| 111 | |
| 112 | #ifdef CONFIG_ARCH_MISC_INIT |
| 113 | int arch_misc_init(void) |
| 114 | { |
| 115 | char qspi_string[13]; |
| 116 | |
| 117 | sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); |
| 118 | env_set("qspi_clock", qspi_string); |
| 119 | |
| 120 | socfpga_set_phymode(); |
| 121 | return 0; |
| 122 | } |
| 123 | #endif |
| 124 | |
| 125 | int arch_early_init_r(void) |
| 126 | { |
| 127 | return 0; |
| 128 | } |
| 129 | |
| 130 | void do_bridge_reset(int enable) |
| 131 | { |
| 132 | socfpga_bridges_reset(enable); |
| 133 | } |