blob: 3f30b6bf972e1551c0afaac42c617fcfa120402f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Stefan Roese6a905952015-04-20 09:31:27 +02002/*
3 * Copyright (C) Marvell International Ltd. and its affiliates
Stefan Roese6a905952015-04-20 09:31:27 +02004 */
5
6#ifndef _CTRL_PEX_H
7#define _CTRL_PEX_H
8
9#include "high_speed_env_spec.h"
10
11/* Sample at Reset */
12#define MPP_SAMPLE_AT_RESET(id) (0xe4200 + (id * 4))
13
14/* PCI Express Control and Status Registers */
15#define MAX_PEX_BUSSES 256
16
17#define MISC_REGS_OFFSET 0x18200
18#define MV_MISC_REGS_BASE MISC_REGS_OFFSET
19#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
20
Stefan Roese61cee0a2015-06-08 17:01:26 +020021#define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \
22 (0x40000 + ((if) - 1) * 0x4000) : \
23 0x80000)
24#define PEX_IF_REGS_BASE(if) (PEX_IF_REGS_OFFSET(if))
Stefan Roese6a905952015-04-20 09:31:27 +020025#define PEX_CAPABILITIES_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x60)
26#define PEX_LINK_CTRL_STATUS2_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x90)
27#define PEX_CTRL_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a00)
28#define PEX_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a04)
29#define PEX_DBG_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a64)
30#define PEX_LINK_CAPABILITY_REG 0x6c
31#define PEX_LINK_CTRL_STAT_REG 0x70
32#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */
33#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS)
34#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */
35#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS)
36
37/* PEX_CAPABILITIES_REG fields */
38#define PCIE0_ENABLE_OFFS 0
39#define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS)
40#define PCIE1_ENABLE_OFFS 1
41#define PCIE1_ENABLE_MASK (0x1 << PCIE1_ENABLE_OFFS)
42#define PCIE2_ENABLE_OFFS 2
43#define PCIE2_ENABLE_MASK (0x1 << PCIE2_ENABLE_OFFS)
44#define PCIE3_ENABLE_OFFS 3
45#define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS)
46
47/* Controller revision info */
48#define PEX_DEVICE_AND_VENDOR_ID 0x000
Chris Packhamd16a6952018-05-10 13:28:26 +120049#define PEX_CFG_DIRECT_ACCESS(if, reg) (PEX_IF_REGS_BASE(if) + (reg))
Stefan Roese6a905952015-04-20 09:31:27 +020050
51/* PCI Express Configuration Address Register */
52#define PXCAR_REG_NUM_OFFS 2
53#define PXCAR_REG_NUM_MAX 0x3f
54#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << \
55 PXCAR_REG_NUM_OFFS)
56#define PXCAR_FUNC_NUM_OFFS 8
57#define PXCAR_FUNC_NUM_MAX 0x7
58#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << \
59 PXCAR_FUNC_NUM_OFFS)
60#define PXCAR_DEVICE_NUM_OFFS 11
61#define PXCAR_DEVICE_NUM_MAX 0x1f
62#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << \
63 PXCAR_DEVICE_NUM_OFFS)
64#define PXCAR_BUS_NUM_OFFS 16
65#define PXCAR_BUS_NUM_MAX 0xff
66#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << \
67 PXCAR_BUS_NUM_OFFS)
68#define PXCAR_EXT_REG_NUM_OFFS 24
69#define PXCAR_EXT_REG_NUM_MAX 0xf
70
71#define PEX_CFG_ADDR_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18f8)
72#define PEX_CFG_DATA_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18fc)
73
74#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
75#define PXCAR_REAL_EXT_REG_NUM_MASK (0xf << PXCAR_REAL_EXT_REG_NUM_OFFS)
76
77#define PXCAR_CONFIG_EN BIT(31)
78#define PEX_STATUS_AND_COMMAND 0x004
79#define PXSAC_MABORT BIT(29) /* Recieved Master Abort */
80
Kevin Smith6406d432015-10-23 17:53:19 +000081int hws_pex_config(const struct serdes_map *serdes_map, u8 count);
Stefan Roese6a905952015-04-20 09:31:27 +020082int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
83int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
84u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off);
85
Mario Sixa3d18342017-01-11 16:00:47 +010086void board_pex_config(void);
87
Stefan Roese6a905952015-04-20 09:31:27 +020088#endif