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git01.mediatek.com / filogic / uboot / 47db6e425fcc2c3560b3671498a98e17c1c51a15 / . / arch / arm / dts / r7s72100.dtsi
blob: 2211f88ede2ad351fdbbd1c2e07865a3448f8a97 [file] [log] [blame]
Chris Brandt43b11d92017-08-23 14:53:59 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r7s72100 SoC
4 *
5 * Copyright (C) 2013-14 Renesas Solutions Corp.
6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
7 */
8
9#include <dt-bindings/clock/r7s72100-clock.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 compatible = "renesas,r7s72100";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 aliases {
19 i2c0 = &i2c0;
20 i2c1 = &i2c1;
21 i2c2 = &i2c2;
22 i2c3 = &i2c3;
23 spi0 = &spi0;
24 spi1 = &spi1;
25 spi2 = &spi2;
26 spi3 = &spi3;
27 spi4 = &spi4;
28 };
29
30 /* Fixed factor clocks */
31 b_clk: b {
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
34 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
35 clock-mult = <1>;
36 clock-div = <3>;
37 };
38
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 cpu@0 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a9";
46 reg = <0>;
47 clock-frequency = <400000000>;
48 clocks = <&cpg_clocks R7S72100_CLK_I>;
49 next-level-cache = <&L2>;
50 };
51 };
52
53 /* External clocks */
54 extal_clk: extal {
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 /* If clk present, value must be set by board */
58 clock-frequency = <0>;
59 };
60
61 p0_clk: p0 {
62 #clock-cells = <0>;
63 compatible = "fixed-factor-clock";
64 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
65 clock-mult = <1>;
66 clock-div = <12>;
67 };
68
69 p1_clk: p1 {
70 #clock-cells = <0>;
71 compatible = "fixed-factor-clock";
72 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
73 clock-mult = <1>;
74 clock-div = <6>;
75 };
76
77 pmu {
78 compatible = "arm,cortex-a9-pmu";
79 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
80 };
81
82 rtc_x1_clk: rtc_x1 {
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
85 /* If clk present, value must be set by board to 32678 */
86 clock-frequency = <0>;
87 };
88
89 rtc_x3_clk: rtc_x3 {
90 #clock-cells = <0>;
91 compatible = "fixed-clock";
92 /* If clk present, value must be set by board to 4000000 */
93 clock-frequency = <0>;
94 };
95
96 soc {
97 compatible = "simple-bus";
98 interrupt-parent = <&gic>;
99
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103
104 L2: cache-controller@3ffff000 {
105 compatible = "arm,pl310-cache";
106 reg = <0x3ffff000 0x1000>;
107 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
108 arm,early-bresp-disable;
109 arm,full-line-zero-disable;
110 cache-unified;
111 cache-level = <2>;
112 };
113
114 scif0: serial@e8007000 {
115 compatible = "renesas,scif-r7s72100", "renesas,scif";
116 reg = <0xe8007000 64>;
117 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
122 clock-names = "fck";
123 power-domains = <&cpg_clocks>;
124 status = "disabled";
125 };
126
127 scif1: serial@e8007800 {
128 compatible = "renesas,scif-r7s72100", "renesas,scif";
129 reg = <0xe8007800 64>;
130 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
135 clock-names = "fck";
136 power-domains = <&cpg_clocks>;
137 status = "disabled";
138 };
139
140 scif2: serial@e8008000 {
141 compatible = "renesas,scif-r7s72100", "renesas,scif";
142 reg = <0xe8008000 64>;
143 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
148 clock-names = "fck";
149 power-domains = <&cpg_clocks>;
150 status = "disabled";
151 };
152
153 scif3: serial@e8008800 {
154 compatible = "renesas,scif-r7s72100", "renesas,scif";
155 reg = <0xe8008800 64>;
156 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
161 clock-names = "fck";
162 power-domains = <&cpg_clocks>;
163 status = "disabled";
164 };
165
166 scif4: serial@e8009000 {
167 compatible = "renesas,scif-r7s72100", "renesas,scif";
168 reg = <0xe8009000 64>;
169 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
174 clock-names = "fck";
175 power-domains = <&cpg_clocks>;
176 status = "disabled";
177 };
178
179 scif5: serial@e8009800 {
180 compatible = "renesas,scif-r7s72100", "renesas,scif";
181 reg = <0xe8009800 64>;
182 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
187 clock-names = "fck";
188 power-domains = <&cpg_clocks>;
189 status = "disabled";
190 };
191
192 scif6: serial@e800a000 {
193 compatible = "renesas,scif-r7s72100", "renesas,scif";
194 reg = <0xe800a000 64>;
195 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
200 clock-names = "fck";
201 power-domains = <&cpg_clocks>;
202 status = "disabled";
203 };
204
205 scif7: serial@e800a800 {
206 compatible = "renesas,scif-r7s72100", "renesas,scif";
207 reg = <0xe800a800 64>;
208 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
213 clock-names = "fck";
214 power-domains = <&cpg_clocks>;
215 status = "disabled";
216 };
217
218 spi0: spi@e800c800 {
219 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
220 reg = <0xe800c800 0x24>;
221 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
224 interrupt-names = "error", "rx", "tx";
225 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
226 power-domains = <&cpg_clocks>;
227 num-cs = <1>;
228 #address-cells = <1>;
229 #size-cells = <0>;
230 status = "disabled";
231 };
232
233 spi1: spi@e800d000 {
234 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
235 reg = <0xe800d000 0x24>;
236 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
239 interrupt-names = "error", "rx", "tx";
240 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
241 power-domains = <&cpg_clocks>;
242 num-cs = <1>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 status = "disabled";
246 };
247
248 spi2: spi@e800d800 {
249 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
250 reg = <0xe800d800 0x24>;
251 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
254 interrupt-names = "error", "rx", "tx";
255 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
256 power-domains = <&cpg_clocks>;
257 num-cs = <1>;
258 #address-cells = <1>;
259 #size-cells = <0>;
260 status = "disabled";
261 };
262
263 spi3: spi@e800e000 {
264 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
265 reg = <0xe800e000 0x24>;
266 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
269 interrupt-names = "error", "rx", "tx";
270 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
271 power-domains = <&cpg_clocks>;
272 num-cs = <1>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 status = "disabled";
276 };
277
278 spi4: spi@e800e800 {
279 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
280 reg = <0xe800e800 0x24>;
281 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "error", "rx", "tx";
285 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
286 power-domains = <&cpg_clocks>;
287 num-cs = <1>;
288 #address-cells = <1>;
289 #size-cells = <0>;
290 status = "disabled";
291 };
292
293 usbhs0: usb@e8010000 {
294 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
295 reg = <0xe8010000 0x1a0>;
296 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&mstp7_clks R7S72100_CLK_USB0>;
298 renesas,buswait = <4>;
299 power-domains = <&cpg_clocks>;
300 status = "disabled";
301 };
302
303 usbhs1: usb@e8207000 {
304 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
305 reg = <0xe8207000 0x1a0>;
306 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&mstp7_clks R7S72100_CLK_USB1>;
308 renesas,buswait = <4>;
309 power-domains = <&cpg_clocks>;
310 status = "disabled";
311 };
312
313 mmcif: mmc@e804c800 {
314 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
315 reg = <0xe804c800 0x80>;
316 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
320 power-domains = <&cpg_clocks>;
321 reg-io-width = <4>;
322 bus-width = <8>;
323 status = "disabled";
324 };
325
326 sdhi0: sd@e804e000 {
327 compatible = "renesas,sdhi-r7s72100";
328 reg = <0xe804e000 0x100>;
329 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
332
333 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
334 <&mstp12_clks R7S72100_CLK_SDHI01>;
335 clock-names = "core", "cd";
336 power-domains = <&cpg_clocks>;
337 cap-sd-highspeed;
338 cap-sdio-irq;
339 status = "disabled";
340 };
341
342 sdhi1: sd@e804e800 {
343 compatible = "renesas,sdhi-r7s72100";
344 reg = <0xe804e800 0x100>;
345 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
348
349 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
350 <&mstp12_clks R7S72100_CLK_SDHI11>;
351 clock-names = "core", "cd";
352 power-domains = <&cpg_clocks>;
353 cap-sd-highspeed;
354 cap-sdio-irq;
355 status = "disabled";
356 };
357
358 gic: interrupt-controller@e8201000 {
359 compatible = "arm,pl390";
360 #interrupt-cells = <3>;
361 #address-cells = <0>;
362 interrupt-controller;
363 reg = <0xe8201000 0x1000>,
364 <0xe8202000 0x1000>;
365 };
366
367 ether: ethernet@e8203000 {
368 compatible = "renesas,ether-r7s72100";
369 reg = <0xe8203000 0x800>,
370 <0xe8204800 0x200>;
371 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
373 power-domains = <&cpg_clocks>;
374 phy-mode = "mii";
375 #address-cells = <1>;
376 #size-cells = <0>;
377 status = "disabled";
378 };
379
380 ceu: camera@e8210000 {
381 reg = <0xe8210000 0x3000>;
382 compatible = "renesas,r7s72100-ceu";
383 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&mstp6_clks R7S72100_CLK_CEU>;
385 power-domains = <&cpg_clocks>;
386 status = "disabled";
387 };
388
389 wdt: watchdog@fcfe0000 {
390 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
391 reg = <0xfcfe0000 0x6>;
392 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&p0_clk>;
394 };
395
396 /* Special CPG clocks */
397 cpg_clocks: cpg_clocks@fcfe0000 {
398 #clock-cells = <1>;
399 compatible = "renesas,r7s72100-cpg-clocks",
400 "renesas,rz-cpg-clocks";
401 reg = <0xfcfe0000 0x18>;
402 clocks = <&extal_clk>, <&usb_x1_clk>;
403 clock-output-names = "pll", "i", "g";
404 #power-domain-cells = <0>;
405 };
406
407 /* MSTP clocks */
408 mstp3_clks: mstp3_clks@fcfe0420 {
409 #clock-cells = <1>;
410 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
411 reg = <0xfcfe0420 4>;
412 clocks = <&p0_clk>;
413 clock-indices = <R7S72100_CLK_MTU2>;
414 clock-output-names = "mtu2";
415 };
416
417 mstp4_clks: mstp4_clks@fcfe0424 {
418 #clock-cells = <1>;
419 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
420 reg = <0xfcfe0424 4>;
421 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
422 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
423 clock-indices = <
424 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
425 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
426 >;
427 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
428 };
429
430 mstp5_clks: mstp5_clks@fcfe0428 {
431 #clock-cells = <1>;
432 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
433 reg = <0xfcfe0428 4>;
434 clocks = <&p0_clk>, <&p0_clk>;
435 clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
436 clock-output-names = "ostm0", "ostm1";
437 };
438
439 mstp6_clks: mstp6_clks@fcfe042c {
440 #clock-cells = <1>;
441 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
442 reg = <0xfcfe042c 4>;
443 clocks = <&b_clk>, <&p0_clk>;
444 clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
445 clock-output-names = "ceu", "rtc";
446 };
447
448 mstp7_clks: mstp7_clks@fcfe0430 {
449 #clock-cells = <1>;
450 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
451 reg = <0xfcfe0430 4>;
452 clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
453 clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
454 clock-output-names = "ether", "usb0", "usb1";
455 };
456
457 mstp8_clks: mstp8_clks@fcfe0434 {
458 #clock-cells = <1>;
459 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
460 reg = <0xfcfe0434 4>;
461 clocks = <&p1_clk>;
462 clock-indices = <R7S72100_CLK_MMCIF>;
463 clock-output-names = "mmcif";
464 };
465
466 mstp9_clks: mstp9_clks@fcfe0438 {
467 #clock-cells = <1>;
468 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
469 reg = <0xfcfe0438 4>;
470 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
471 clock-indices = <
472 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
473 >;
474 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
475 };
476
477 mstp10_clks: mstp10_clks@fcfe043c {
478 #clock-cells = <1>;
479 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
480 reg = <0xfcfe043c 4>;
481 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
482 <&p1_clk>;
483 clock-indices = <
484 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
485 R7S72100_CLK_SPI4
486 >;
487 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
488 };
489 mstp12_clks: mstp12_clks@fcfe0444 {
490 #clock-cells = <1>;
491 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
492 reg = <0xfcfe0444 4>;
493 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
494 clock-indices = <
495 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
496 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
497 >;
498 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
499 };
500
501 pinctrl: pin-controller@fcfe3000 {
502 compatible = "renesas,r7s72100-ports";
503
504 reg = <0xfcfe3000 0x4230>;
505
506 port0: gpio-0 {
507 gpio-controller;
508 #gpio-cells = <2>;
509 gpio-ranges = <&pinctrl 0 0 6>;
510 };
511
512 port1: gpio-1 {
513 gpio-controller;
514 #gpio-cells = <2>;
515 gpio-ranges = <&pinctrl 0 16 16>;
516 };
517
518 port2: gpio-2 {
519 gpio-controller;
520 #gpio-cells = <2>;
521 gpio-ranges = <&pinctrl 0 32 16>;
522 };
523
524 port3: gpio-3 {
525 gpio-controller;
526 #gpio-cells = <2>;
527 gpio-ranges = <&pinctrl 0 48 16>;
528 };
529
530 port4: gpio-4 {
531 gpio-controller;
532 #gpio-cells = <2>;
533 gpio-ranges = <&pinctrl 0 64 16>;
534 };
535
536 port5: gpio-5 {
537 gpio-controller;
538 #gpio-cells = <2>;
539 gpio-ranges = <&pinctrl 0 80 11>;
540 };
541
542 port6: gpio-6 {
543 gpio-controller;
544 #gpio-cells = <2>;
545 gpio-ranges = <&pinctrl 0 96 16>;
546 };
547
548 port7: gpio-7 {
549 gpio-controller;
550 #gpio-cells = <2>;
551 gpio-ranges = <&pinctrl 0 112 16>;
552 };
553
554 port8: gpio-8 {
555 gpio-controller;
556 #gpio-cells = <2>;
557 gpio-ranges = <&pinctrl 0 128 16>;
558 };
559
560 port9: gpio-9 {
561 gpio-controller;
562 #gpio-cells = <2>;
563 gpio-ranges = <&pinctrl 0 144 8>;
564 };
565
566 port10: gpio-10 {
567 gpio-controller;
568 #gpio-cells = <2>;
569 gpio-ranges = <&pinctrl 0 160 16>;
570 };
571
572 port11: gpio-11 {
573 gpio-controller;
574 #gpio-cells = <2>;
575 gpio-ranges = <&pinctrl 0 176 16>;
576 };
577 };
578
579 ostm0: timer@fcfec000 {
580 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
581 reg = <0xfcfec000 0x30>;
582 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
583 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
584 power-domains = <&cpg_clocks>;
585 status = "disabled";
586 };
587
588 ostm1: timer@fcfec400 {
589 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
590 reg = <0xfcfec400 0x30>;
591 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
592 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
593 power-domains = <&cpg_clocks>;
594 status = "disabled";
595 };
596
597 i2c0: i2c@fcfee000 {
598 #address-cells = <1>;
599 #size-cells = <0>;
600 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
601 reg = <0xfcfee000 0x44>;
602 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
604 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
605 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
611 clock-frequency = <100000>;
612 power-domains = <&cpg_clocks>;
613 status = "disabled";
614 };
615
616 i2c1: i2c@fcfee400 {
617 #address-cells = <1>;
618 #size-cells = <0>;
619 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
620 reg = <0xfcfee400 0x44>;
621 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
623 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
624 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
630 clock-frequency = <100000>;
631 power-domains = <&cpg_clocks>;
632 status = "disabled";
633 };
634
635 i2c2: i2c@fcfee800 {
636 #address-cells = <1>;
637 #size-cells = <0>;
638 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
639 reg = <0xfcfee800 0x44>;
640 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
642 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
643 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
649 clock-frequency = <100000>;
650 power-domains = <&cpg_clocks>;
651 status = "disabled";
652 };
653
654 i2c3: i2c@fcfeec00 {
655 #address-cells = <1>;
656 #size-cells = <0>;
657 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
658 reg = <0xfcfeec00 0x44>;
659 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
661 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
662 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
668 clock-frequency = <100000>;
669 power-domains = <&cpg_clocks>;
670 status = "disabled";
671 };
672
673 mtu2: timer@fcff0000 {
674 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
675 reg = <0xfcff0000 0x400>;
676 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
677 interrupt-names = "tgi0a";
678 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
679 clock-names = "fck";
680 power-domains = <&cpg_clocks>;
681 status = "disabled";
682 };
683
684 rtc: rtc@fcff1000 {
685 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
686 reg = <0xfcff1000 0x2e>;
687 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
690 interrupt-names = "alarm", "period", "carry";
691 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
692 <&rtc_x3_clk>, <&extal_clk>;
693 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
694 power-domains = <&cpg_clocks>;
695 status = "disabled";
696 };
697 };
698
699 usb_x1_clk: usb_x1 {
700 #clock-cells = <0>;
701 compatible = "fixed-clock";
702 /* If clk present, value must be set by board */
703 clock-frequency = <0>;
704 };
705};