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Marcel Ziswiler315deb32023-08-04 12:08:08 +02001// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2023 Toradex
4 */
5
6#include "k3-am625-verdin-wifi-dev-binman.dtsi"
7
8/ {
9 aliases {
10 eeprom0 = &eeprom_module;
11 eeprom1 = &eeprom_carrier_board;
12 eeprom2 = &eeprom_display_adapter;
13 };
14
15 chosen {
16 tick-timer = &main_timer0;
17 };
18
19 memory@80000000 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020020 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020021 };
22};
23
24&cbass_main {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020025 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020026
27 timer@2400000 {
28 clock-frequency = <25000000>;
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020029 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020030 };
31};
32
33&cbass_mcu {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020034 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020035};
36
37&cbass_wakeup {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020038 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020039};
40
41&chipid {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020042 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020043};
44
45&cpsw3g {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020046 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020047};
48
49&cpsw3g_phy0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020050 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020051};
52
53&cpsw3g_phy1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020054 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020055};
56
57&cpsw_port1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020058 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020059};
60
61&cpsw_port2 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020062 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020063};
64
65/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
66&cpsw3g_mdio {
67 /delete-property/ assigned-clocks;
68 /delete-property/ assigned-clock-parents;
69 /delete-property/ assigned-clock-rates;
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020070 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020071};
72
73&dmsc {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020074 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020075
76 k3_sysreset: sysreset-controller {
77 compatible = "ti,sci-sysreset";
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020078 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020079 };
80};
81
82&dmss {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020083 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020084};
85
86&fss {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020087 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020088};
89
90&k3_clks {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020091 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020092};
93
94&k3_pds {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020095 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +020096};
97
98&k3_reset {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +020099 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200100};
101
102&main_gpio0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200103 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200104};
105
106/* On-module I2C - PMIC_I2C */
107&main_i2c0 {
108 eeprom_module: eeprom@50 {
109 compatible = "i2c-eeprom";
110 pagesize = <16>;
111 reg = <0x50>;
112 };
113};
114
115/* Verdin I2C_1 */
116&main_i2c1 {
117 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
118 eeprom_display_adapter: eeprom@50 {
119 compatible = "i2c-eeprom";
120 reg = <0x50>;
121 pagesize = <16>;
122 };
123
124 /* EEPROM on carrier board */
125 eeprom_carrier_board: eeprom@57 {
126 compatible = "i2c-eeprom";
127 reg = <0x57>;
128 pagesize = <16>;
129 };
130};
131
132&main_pmx0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200133 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200134};
135
136/* Verdin UART_3, used as the Linux console */
137&main_uart0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200138 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200139};
140
141/* Verdin UART_1 */
142&main_uart1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200143 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200144};
145
146&mcu_pmx0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200147 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200148};
149
150&pinctrl_ctrl_sleep_moci {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200151 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200152};
153
154&pinctrl_i2c0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200155 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200156};
157
158&pinctrl_i2c1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200159 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200160};
161
162&pinctrl_sdhci0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200163 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200164};
165
166&pinctrl_uart0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200167 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200168};
169
170&pinctrl_uart1 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200171 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200172};
173
174&pinctrl_wkup_uart0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200175 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200176};
177
178&sdhci0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200179 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200180};
181
182&sdhci2 {
183 status = "disabled";
184};
185
186&secure_proxy_main {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200187 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200188};
189
190&verdin_ctrl_sleep_moci {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200191 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200192};
193
194&wkup_conf {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200195 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200196};
197
198/* Verdin UART_2 */
199&wkup_uart0 {
Marcel Ziswilerddaf8ab2023-10-10 13:13:04 +0200200 bootph-all;
Marcel Ziswiler315deb32023-08-04 12:08:08 +0200201};