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git01.mediatek.com / filogic / uboot / 47bb3068d073547e3e51494b3068c0b3772ee9e0 / . / board / amcc / canyonlands / init.S
blob: bf00bd6bcaa186e802158363b861e9fe70d9a012 [file] [log] [blame]
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]1/*
2 * (C) Copyright 2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]6 */
7
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]8#include <asm-offsets.h>
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]9#include <ppc_asm.tmpl>
10#include <config.h>
Peter Tyser133c0fe2010-04-12 22:28:07 -0500[diff] [blame]11#include <asm/mmu.h>
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]12
13/**************************************************************************
14 * TLB TABLE
15 *
16 * This table is used by the cpu boot code to setup the initial tlb
17 * entries. Rather than make broad assumptions in the cpu source tree,
18 * this table lets each board set things up however they like.
19 *
20 * Pointer to the table is returned in r1
21 *
22 *************************************************************************/
23 .section .bootpg,"ax"
24 .globl tlbtab
25
26tlbtab:
27 tlbtab_start
28
29 /*
30 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
31 * use the speed up boot process. It is patched after relocation to
32 * enable SA_I
33 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]34 tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]35
36 /*
37 * TLB entries for SDRAM are not needed on this platform.
38 * They are dynamically generated in the SPD DDR(2) detection
39 * routine.
40 */
41
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]42#ifdef CONFIG_SYS_INIT_RAM_DCACHE
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]43 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]44 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]45#endif
46
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]47 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
48 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG)
49 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]50
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]51 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
52 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
53 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
54 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]55
56 /* PCIe UTL register */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]57 tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_RW | SA_IG)
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]58
Adam Graham4900ed22008-10-08 10:12:53 -0700[diff] [blame]59#if !defined(CONFIG_ARCHES)
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]60 /* TLB-entry for NAND */
Felix Radensky19350202011-01-02 11:07:34 +0200[diff] [blame]61 tlbentry(CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG)
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]62
63 /* TLB-entry for CPLD */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]64 tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG)
Adam Graham4900ed22008-10-08 10:12:53 -0700[diff] [blame]65#else
66 /* TLB-entry for FPGA */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]67 tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_RW | SA_IG)
Adam Graham4900ed22008-10-08 10:12:53 -0700[diff] [blame]68#endif
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]69
70 /* TLB-entry for OCM */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]71 tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_RWX | SA_I)
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]72
73 /* TLB-entry for Local Configuration registers => peripherals */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]74 tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]75
Stefan Roese8d0f6b22008-03-05 12:31:53 +0100[diff] [blame]76 /* AHB: Internal USB Peripherals (USB, SATA) */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]77 tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_RWX | SA_IG)
Stefan Roese8d0f6b22008-03-05 12:31:53 +0100[diff] [blame]78
Adam Graham4900ed22008-10-08 10:12:53 -0700[diff] [blame]79#if defined(CONFIG_RAPIDIO)
Wolfgang Denk82f15f32008-11-02 16:14:22 +0100[diff] [blame]80 /* TLB-entries for RapidIO (SRIO) */
Adam Graham4900ed22008-10-08 10:12:53 -0700[diff] [blame]81 tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]82 0xD, AC_RW | SA_IG)
Adam Graham4900ed22008-10-08 10:12:53 -0700[diff] [blame]83 tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]84 0xD, AC_RW | SA_IG)
Adam Graham4900ed22008-10-08 10:12:53 -0700[diff] [blame]85 tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]86 0xD, AC_RW | SA_IG)
Adam Graham4900ed22008-10-08 10:12:53 -0700[diff] [blame]87 tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K, 0x00100000,
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]88 0x4, AC_RW | SA_IG)
Adam Graham4900ed22008-10-08 10:12:53 -0700[diff] [blame]89#endif
90
Stefan Roese105350e2008-03-11 16:51:17 +0100[diff] [blame]91 tlbtab_end