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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese93e6bf42014-10-22 12:13:17 +02002/*
3 * (C) Copyright 2011
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Lei Wen <leiwen@marvell.com>
Stefan Roese93e6bf42014-10-22 12:13:17 +02006 */
7
8/*
9 * This file should be included in board config header file.
10 *
Stefan Roese7cd34842015-04-25 06:29:49 +020011 * It supports common definitions for MVEBU platforms
Stefan Roese93e6bf42014-10-22 12:13:17 +020012 */
13
Stefan Roeseebda3ec2015-04-25 06:29:47 +020014#ifndef _MVEBU_CONFIG_H
15#define _MVEBU_CONFIG_H
Stefan Roese93e6bf42014-10-22 12:13:17 +020016
17#include <asm/arch/soc.h>
18
Stefan Roese479f9af2016-02-10 07:23:00 +010019#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \
Chris Packhama8f845e2019-04-11 22:22:50 +120020 || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
Stefan Roeseeb083e52015-12-21 13:56:33 +010021/*
22 * Set this for the common xor register definitions needed in dram.c
23 * for A38x as well here.
24 */
Stefan Roese93e6bf42014-10-22 12:13:17 +020025#define MV88F78X60 /* for the DDR training bin_hdr code */
Stefan Roese7cd34842015-04-25 06:29:49 +020026#endif
Stefan Roese93e6bf42014-10-22 12:13:17 +020027
Stefan Roesec14c93f2015-11-18 12:44:29 +010028#define CONFIG_SYS_L2_PL310
29
30#ifdef CONFIG_SPL_BUILD
31#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
32#endif
33
Stefan Roese93e6bf42014-10-22 12:13:17 +020034/*
Baruch Siachea3d9de2018-06-18 21:56:25 +030035 * By default the generated mvebu kwbimage.cfg is used
Stefan Roese93e6bf42014-10-22 12:13:17 +020036 * If for some board, different configuration file need to be used,
37 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
38 */
39#ifndef CONFIG_SYS_KWD_CONFIG
Baruch Siachea3d9de2018-06-18 21:56:25 +030040#define CONFIG_SYS_KWD_CONFIG arch/arm/mach-mvebu/kwbimage.cfg
Stefan Roese93e6bf42014-10-22 12:13:17 +020041#endif /* CONFIG_SYS_KWD_CONFIG */
42
Stefan Roese93e6bf42014-10-22 12:13:17 +020043/* end of 16M scrubbed by training in bootrom */
44#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
Stefan Roese93e6bf42014-10-22 12:13:17 +020045
46#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
47
Stefan Roese49e7d772015-11-20 13:51:57 +010048/* Needed for SPI NOR booting in SPL */
49#define CONFIG_DM_SEQ_ALIAS 1
50
Stefan Roese93e6bf42014-10-22 12:13:17 +020051/*
52 * Ethernet Driver configuration
53 */
54#ifdef CONFIG_CMD_NET
Stefan Roese93e6bf42014-10-22 12:13:17 +020055#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
Stefan Roeseb3efc572015-11-24 09:15:22 +010056#define CONFIG_ARP_TIMEOUT 200
57#define CONFIG_NET_RETRY_COUNT 50
Stefan Roese93e6bf42014-10-22 12:13:17 +020058#endif /* CONFIG_CMD_NET */
59
60/*
61 * I2C related stuff
62 */
63#ifdef CONFIG_CMD_I2C
64#ifndef CONFIG_SYS_I2C_SOFT
65#define CONFIG_I2C_MVTWSI
66#endif
67#define CONFIG_SYS_I2C_SLAVE 0x0
68#define CONFIG_SYS_I2C_SPEED 100000
69#endif
70
Stefan Roese64174892015-10-22 12:36:31 +020071/* Use common timer */
72#define CONFIG_SYS_TIMER_COUNTS_DOWN
73#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
74#define CONFIG_SYS_TIMER_RATE 25000000
75
Stefan Roeseebda3ec2015-04-25 06:29:47 +020076#endif /* __MVEBU_CONFIG_H */