blob: 20ae011ecac16722782b521577d1b7327f2c4d6a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Peng Fan81590632016-08-11 14:02:57 +08002/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
Peng Fan81590632016-08-11 14:02:57 +08004 */
5
6#include <asm/arch/clock.h>
7#include <asm/arch/iomux.h>
8#include <asm/arch/imx-regs.h>
9#include <asm/arch/crm_regs.h>
10#include <asm/arch/mx6-pins.h>
11#include <asm/arch/sys_proto.h>
12#include <asm/gpio.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020013#include <asm/mach-imx/iomux-v3.h>
14#include <asm/mach-imx/boot_mode.h>
Peng Fan81590632016-08-11 14:02:57 +080015#include <asm/io.h>
16#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060017#include <env.h>
Yangbo Lu73340382019-06-21 11:42:28 +080018#include <fsl_esdhc_imx.h>
Peng Fan81590632016-08-11 14:02:57 +080019#include <linux/sizes.h>
20#include <mmc.h>
21
22DECLARE_GLOBAL_DATA_PTR;
23
24#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
25 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
26 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
27
28int dram_init(void)
29{
30 gd->ram_size = imx_ddr_size();
31
32 return 0;
33}
34
35static iomux_v3_cfg_t const uart1_pads[] = {
36 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
37 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
38};
39
40static void setup_iomux_uart(void)
41{
42 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
43}
44
45int board_mmc_get_env_dev(int devno)
46{
47 return devno;
48}
49
50int mmc_map_to_kernel_blk(int devno)
51{
52 return devno;
53}
54
55int board_early_init_f(void)
56{
57 setup_iomux_uart();
58
59 return 0;
60}
61
62int board_init(void)
63{
64 /* Address of boot parameters */
65 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
66
67 return 0;
68}
69
70#ifdef CONFIG_CMD_BMODE
71static const struct boot_mode board_boot_modes[] = {
72 /* 4 bit bus width */
73 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
74 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
75 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
76 {NULL, 0},
77};
78#endif
79
80int board_late_init(void)
81{
82#ifdef CONFIG_CMD_BMODE
83 add_board_boot_modes(board_boot_modes);
84#endif
85
86#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
Peng Fan5098eae2019-08-08 09:55:57 +000087 if (is_cpu_type(MXC_CPU_MX6ULZ))
88 env_set("board_name", "ULZ-EVK");
89 else
90 env_set("board_name", "EVK");
Simon Glass6a38e412017-08-03 12:22:09 -060091 env_set("board_rev", "14X14");
Peng Fan81590632016-08-11 14:02:57 +080092#endif
93
94 return 0;
95}
96
97int checkboard(void)
98{
Peng Fan5098eae2019-08-08 09:55:57 +000099 if (is_cpu_type(MXC_CPU_MX6ULZ))
100 puts("Board: MX6ULZ 14x14 EVK\n");
101 else
102 puts("Board: MX6ULL 14x14 EVK\n");
Peng Fan81590632016-08-11 14:02:57 +0800103
104 return 0;
105}