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git01.mediatek.com / filogic / uboot / 4767923aab7157bc735732614f3e29eb2beb5c3a / . / arch / powerpc / cpu / mpc85xx / p4080_serdes.c
blob: e719d322ee4ccdb1b969b729881216cf924368ab [file] [log] [blame]
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]1/*
2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]5 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/fsl_serdes.h>
10#include <asm/processor.h>
11#include <asm/io.h>
12#include "fsl_corenet_serdes.h"
13
14static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
15 [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
16 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
17 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
18 [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
19 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
20 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
21 [0x8] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
22 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
23 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
24 [0xd] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
25 SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
26 XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
27 [0xe] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
28 SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
29 XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
30 [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
31 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2,
32 XAUI_FM2, XAUI_FM2, XAUI_FM2, NONE, NONE, NONE, NONE},
33 [0x10] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM2_DTSEC1,
34 SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
35 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
36 NONE, NONE, NONE, NONE},
37 [0x13] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
38 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
39 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
40 [0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
41 AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
42 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
43 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
44 [0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
45 AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
46 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
47 [0x1d] = {PCIE1, PCIE1, PCIE3, PCIE3, NONE, SRIO2, NONE, SRIO1,
48 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
49 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
50 [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
51 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
52 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
53 [0x25] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
54 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
55 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
56};
57
Kumar Gala779a5322010-07-13 00:39:46 -0500[diff] [blame]58#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
59uint16_t srds_lpd_b[SRDS_MAX_BANK];
60#endif
61
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]62enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
63{
64 if (!serdes_lane_enabled(lane))
65 return NONE;
66
67 return serdes_cfg_tbl[cfg][lane];
68}
69
70int is_serdes_prtcl_valid(u32 prtcl) {
71 int i;
72
Axel Linab95b092013-05-26 15:00:30 +0800[diff] [blame]73 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]74 return 0;
75
76 for (i = 0; i < SRDS_MAX_LANES; i++) {
77 if (serdes_cfg_tbl[prtcl][i] != NONE)
78 return 1;
79 }
80
81 return 0;
82}